ADD, ADDS (SP plus immediate) -- AArch32

ADD, ADDS (SP plus immediate)

Add to SP (immediate) adds an immediate value to the SP value, and writes the result to the destination register.

If the destination register is not the PC, the ADDS variant of the instruction updates the condition flags based on the result.

The field descriptions for <Rd> identify the encodings where the PC is permitted as the destination register. However, when the destination register is the PC:

The ADD variant of the instruction is an interworking branch, see Pseudocode description of operations on the AArch32 general-purpose registers and the PC.
The ADDS variant of the instruction performs an exception return without the use of the stack. Arm deprecates use of this instruction. However, in this case:
- The PE branches to the address written to the PC, and restores PSTATE from SPSR_<current_mode>.
- The PE checks SPSR_<current_mode> for an illegal return event. See Illegal return events from AArch32 state.
- The instruction is undefined in Hyp mode.
- The instruction is constrained unpredictable in User mode and System mode.

It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 , T2 , T3 and T4 ) .

A1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
!= 1111				0	0	1	0	1	0	0	S	1	1	0	1	Rd				imm12
cond

ADDS (S == 1)

ADDS{<c>}{<q>} {<Rd>,} SP, #<const>

constant d = UInt(Rd); constant setflags = (S == '1'); constant imm32 = A32ExpandImm(imm12);

T1

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
1	0	1	0	1	Rd			imm8

T1

ADD{<c>}{<q>} <Rd>, SP, #<imm8>

constant d = UInt(Rd); constant setflags = FALSE; constant imm32 = ZeroExtend(imm8:'00', 32);

T2

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
1	0	1	1	0	0	0	0	0	imm7

T2

ADD{<c>}{<q>} {SP,} SP, #<imm7>

constant d = 13; constant setflags = FALSE; constant imm32 = ZeroExtend(imm7:'00', 32);

T3

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
1	1	1	1	0	i	0	1	0	0	0	S	1	1	0	1	0	imm3			Rd				imm8

ADD (S == 0)

ADD{<c>}.W {<Rd>,} SP, #<const> // (<Rd>, <const> can be represented in T1 or T2)

ADD{<c>}{<q>} {<Rd>,} SP, #<const>

ADDS (S == 1 && Rd != 1111)

ADDS{<c>}{<q>} {<Rd>,} SP, #<const>

if Rd == '1111' && S == '1' then SEE "CMN (immediate)"; constant d = UInt(Rd); constant setflags = (S == '1'); constant imm32 = T32ExpandImm(i:imm3:imm8); if d == 15 && !setflags then UNPREDICTABLE;

T4

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
1	1	1	1	0	i	1	0	0	0	0	0	1	1	0	1	0	imm3			Rd				imm8

T4

ADD{<c>}{<q>} {<Rd>,} SP, #<imm12> // (<imm12> cannot be represented in T1, T2, or T3)

ADDW{<c>}{<q>} {<Rd>,} SP, #<imm12> // (<imm12> can be represented in T1, T2, or T3)

constant d = UInt(Rd); constant setflags = FALSE; constant imm32 = ZeroExtend(i:imm3:imm8, 32); if d == 15 then UNPREDICTABLE;

For more information about the constrained unpredictable behavior, see Architectural Constraints on UNPREDICTABLE behaviors.

Assembler Symbols

<c>	See Standard assembler syntax fields.

<q>	See Standard assembler syntax fields.

SP,	Is the stack pointer.

<imm7>

Is the unsigned immediate, a multiple of 4, in the range 0 to 508, encoded in the "imm7" field as <imm7>/4.

<Rd>	For encoding A1: is the general-purpose destination register, encoded in the "Rd" field. If omitted, this register is the SP. Arm deprecates using the PC as the destination register, but if the PC is used: For the ADD variant, the instruction is a branch to the address calculated by the operation. This is an interworking branch, see Pseudocode description of operations on the AArch32 general-purpose registers and the PC. For the ADDS variant, the instruction performs an exception return, that restores PSTATE from SPSR_<current_mode>.
	For encoding T1: is the general-purpose destination register, encoded in the "Rd" field.
	For encoding T3 and T4: is the general-purpose destination register, encoded in the "Rd" field. If omitted, this register is the SP.

<imm8>

Is an unsigned immediate, a multiple of 4, in the range 0 to 1020, encoded in the "imm8" field as <imm8>/4.

<imm12>

Is a 12-bit unsigned immediate, in the range 0 to 4095, encoded in the "i:imm3:imm8" field.

<const>	For encoding A1: an immediate value. See Modified immediate constants in A32 instructions for the range of values.
	For encoding T3: an immediate value. See Modified immediate constants in T32 instructions for the range of values.

Operation

if ConditionPassed() then EncodingSpecificOperations(); constant (result, nzcv) = AddWithCarry(R[13], imm32, '0'); if d == 15 then // Can only occur for A32 encoding if setflags then ALUExceptionReturn(result); else ALUWritePC(result); else R[d] = result; if setflags then PSTATE.<N,Z,C,V> = nzcv;

Internal version only: isa v01_31, pseudocode v2024-03_rel ; Build timestamp: 2024-03-25T10:05