Arithmetic Shift Right (immediate) shifts a register value right by an immediate number of bits, shifting in copies of its sign bit, and writes the result to the destination register.
This is an alias of MOV, MOVS (register). This means:
It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T2 and T3 ) .
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| != 1111 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | (0) | (0) | (0) | (0) | Rd | imm5 | 1 | 0 | 0 | Rm | |||||||||||||
| cond | S | stype | |||||||||||||||||||||||||||||
ASR{<c>}{<q>} {<Rd>,} <Rm>, #<imm>
is equivalent to
MOV{<c>}{<q>} <Rd>, <Rm>, ASR #<imm>
and is always the preferred disassembly.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 0 | 0 | 1 | 0 | imm5 | Rm | Rd | ||||||||
| op | |||||||||||||||
ASR<c>{<q>} {<Rd>,} <Rm>, #<imm> // (Inside IT block)
is equivalent to
MOV<c>{<q>} <Rd>, <Rm>, ASR #<imm>
and is the preferred disassembly when InITBlock().
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | (0) | imm3 | Rd | imm2 | 1 | 0 | Rm | |||||||||
| S | stype | ||||||||||||||||||||||||||||||
ASR<c>.W {<Rd>,} <Rm>, #<imm> // (Inside IT block, and <Rd>, <Rm>, <imm> can be represented in T2)
ASR{<c>}{<q>} {<Rd>,} <Rm>, #<imm>
is equivalent to
MOV{<c>}{<q>} <Rd>, <Rm>, ASR #<imm>
and is always the preferred disassembly.
| <c> |
| <q> |
| <Rd> |
For encoding A1: is the general-purpose destination register, encoded in the "Rd" field. Arm deprecates using the PC as the destination register, but if the PC is used, the instruction is a branch to the address calculated by the operation. This is an interworking branch, see Pseudocode description of operations on the AArch32 general-purpose registers and the PC. |
|
For encoding T2 and T3: is the general-purpose destination register, encoded in the "Rd" field. |
The description of MOV, MOVS (register) gives the operational pseudocode for this instruction.
Internal version only: isa v01_31, pseudocode v2024-03_rel ; Build timestamp: 2024-03-25T10:05
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