B -- AArch32

It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 , T2 , T3 and T4 ) .

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
1	1	0	1	!= 111x	imm8
	cond

if cond == '1110' then SEE "UDF"; if cond == '1111' then SEE "SVC"; constant imm32 = SignExtend(imm8:'0', 32); if InITBlock() then UNPREDICTABLE;

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
1	1	1	0	0	imm11

T3

B <c>.W <label> // (Not permitted in IT block, and <label> can be represented in T1)

B<c>{<q>} <label> // (Not permitted in IT block)

if cond<3:1> == '111' then SEE "Related encodings"; constant imm32 = SignExtend(S:J2:J1:imm6:imm11:'0', 32); if InITBlock() then UNPREDICTABLE;

T4

B{<c>}.W <label> // (<label> can be represented in T2)

B{<c>}{<q>} <label>

constant I1 = NOT(J1 EOR S); constant I2 = NOT(J2 EOR S); constant imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32); if InITBlock() && !LastInITBlock() then UNPREDICTABLE;

For more information about the constrained unpredictable behavior, see Architectural Constraints on UNPREDICTABLE behaviors.

Related encodings: Branches and miscellaneous control.

Assembler Symbols

<c>	For encoding A1, T2 and T4: see Standard assembler syntax fields.
	For encoding T1: see Standard assembler syntax fields. Must not be AL or omitted.
	For encoding T3: see Standard assembler syntax fields. <c> must not be AL or omitted.

<q>	See Standard assembler syntax fields.

<label>	For encoding A1: the label of the instruction that is to be branched to. The assembler calculates the required value of the offset from the PC value of the B instruction to this label, then selects an encoding that sets imm32 to that offset. Permitted offsets are multiples of 4 in the range –33554432 to 33554428.
	For encoding T1: the label of the instruction that is to be branched to. The assembler calculates the required value of the offset from the PC value of the B instruction to this label, then selects an encoding that sets imm32 to that offset. Permitted offsets are even numbers in the range –256 to 254.
	For encoding T2: the label of the instruction that is to be branched to. The assembler calculates the required value of the offset from the PC value of the B instruction to this label, then selects an encoding that sets imm32 to that offset. Permitted offsets are even numbers in the range –2048 to 2046.
	For encoding T3: the label of the instruction that is to be branched to. The assembler calculates the required value of the offset from the PC value of the B instruction to this label, then selects an encoding that sets imm32 to that offset. Permitted offsets are even numbers in the range –1048576 to 1048574.
	For encoding T4: the label of the instruction that is to be branched to. The assembler calculates the required value of the offset from the PC value of the B instruction to this label, then selects an encoding that sets imm32 to that offset. Permitted offsets are even numbers in the range –16777216 to 16777214.

Operation

if ConditionPassed() then EncodingSpecificOperations(); BranchWritePC(PC32 + imm32, BranchType_DIR);

Internal version only: isa v01_31, pseudocode v2024-03_rel ; Build timestamp: 2024-03-25T10:05

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
!= 1111				1	0	1	0	imm24
cond

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
1	1	1	1	0	S	!= 111x				imm6						1	0	J1	0	J2	imm11
						cond

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
1	1	1	1	0	S	imm10										1	0	J1	1	J2	imm11