BFI -- AArch32

BFI

Bit Field Insert copies any number of low order bits from a register into the same number of adjacent bits at any position in the destination register.

It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .

A1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
!= 1111				0	1	1	1	1	1	0	msb					Rd				lsb					0	0	1	!= 1111
cond																												Rn

A1

BFI{<c>}{<q>} <Rd>, <Rn>, #<lsb>, #<width>

if Rn == '1111' then SEE "BFC"; constant d = UInt(Rd); constant n = UInt(Rn); constant integer msbit = UInt(msb); constant integer lsbit = UInt(lsb); if d == 15 then UNPREDICTABLE; if msbit < lsbit then UNPREDICTABLE;

CONSTRAINED UNPREDICTABLE behavior

If msbit < lsbit, then one of the following behaviors must occur:

The instruction is undefined.
The instruction executes as NOP.
The value in the destination register is unknown.

T1

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
1	1	1	1	0	(0)	1	1	0	1	1	0	!= 1111				0	imm3			Rd				imm2		(0)	msb
												Rn

T1

BFI{<c>}{<q>} <Rd>, <Rn>, #<lsb>, #<width>

if Rn == '1111' then SEE "BFC"; constant d = UInt(Rd); constant n = UInt(Rn); constant integer msbit = UInt(msb); constant integer lsbit = UInt(imm3:imm2); // Armv8-A removes UNPREDICTABLE for R13 if d == 15 then UNPREDICTABLE; if msbit < lsbit then UNPREDICTABLE;

CONSTRAINED UNPREDICTABLE behavior

If msbit < lsbit, then one of the following behaviors must occur:

The instruction is undefined.
The instruction executes as NOP.
The value in the destination register is unknown.

For more information about the constrained unpredictable behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors.

Assembler Symbols

<c>	See Standard assembler syntax fields.

<q>	See Standard assembler syntax fields.

<Rd>	Is the general-purpose destination register, encoded in the "Rd" field.

<Rn>	Is the general-purpose source register, encoded in the "Rn" field.

<lsb>	For encoding A1: is the least significant destination bit, in the range 0 to 31, encoded in the "lsb" field.
	For encoding T1: is the least significant destination bit, in the range 0 to 31, encoded in the "imm3:imm2" field.

<width>

Is the number of bits to be copied, in the range 1 to 32-<lsb>, encoded in the "msb" field as <lsb>+<width>-1.

Operation

if ConditionPassed() then EncodingSpecificOperations(); R[d]<msbit:lsbit> = R[n]<(msbit-lsbit):0>; // Other bits of R[d] are unchanged

Operational information

If CPSR.DIT is 1, this instruction has passed its condition execution check, and does not use R15 as either its source or destination:

The execution time of this instruction is independent of:
- The values of the data supplied in any of its registers.
- The values of the NZCV flags.
The response of this instruction to asynchronous exceptions does not vary based on:
- The values of the data supplied in any of its registers.
- The values of the NZCV flags.

Internal version only: isa v01_31, pseudocode v2024-03_rel ; Build timestamp: 2024-03-25T10:05