BL, BLX (immediate) -- AArch32

BL, BLX (immediate)

Branch with Link calls a subroutine at a PC-relative address, and setting LR to the return address.

Branch with Link and Exchange Instruction Sets (immediate) calls a subroutine at a PC-relative address, setting LR to the return address, and changes the instruction set from A32 to T32, or from T32 to A32.

It has encodings from the following instruction sets: A32 ( A1 and A2 ) and T32 ( T1 and T2 ) .

A1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
!= 1111				1	0	1	1	imm24
cond

A1

BL{<c>}{<q>} <label>

constant imm32 = SignExtend(imm24:'00', 32); constant targetInstrSet = InstrSet_A32;

A2

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
1	1	1	1	1	0	1	H	imm24
cond

A2

BLX{<c>}{<q>} <label>

constant imm32 = SignExtend(imm24:H:'0', 32); constant targetInstrSet = InstrSet_T32;

T1

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
1	1	1	1	0	S	imm10										1	1	J1	1	J2	imm11

T1

BL{<c>}{<q>} <label>

constant I1 = NOT(J1 EOR S); constant I2 = NOT(J2 EOR S); constant imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32); constant targetInstrSet = InstrSet_T32; if InITBlock() && !LastInITBlock() then UNPREDICTABLE;

T2

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
1	1	1	1	0	S	imm10H										1	1	J1	0	J2	imm10L										H

T2

BLX{<c>}{<q>} <label>

if H == '1' then UNDEFINED; constant I1 = NOT(J1 EOR S); constant I2 = NOT(J2 EOR S); constant imm32 = SignExtend(S:I1:I2:imm10H:imm10L:'00', 32); constant targetInstrSet = InstrSet_A32; if InITBlock() && !LastInITBlock() then UNPREDICTABLE;

For more information about the constrained unpredictable behavior, see Architectural Constraints on UNPREDICTABLE behaviors.

Assembler Symbols

<c>	For encoding A1, T1 and T2: see Standard assembler syntax fields.
	For encoding A2: see Standard assembler syntax fields. <c> must be AL or omitted.

<q>	See Standard assembler syntax fields.

<label>	For encoding A1: the label of the instruction that is to be branched to. The assembler calculates the required value of the offset from the PC value of the BL instruction to this label, then selects an encoding that sets imm32 to that offset. Permitted offsets are multiples of 4 in the range –33554432 to 33554428.
	For encoding A2: the label of the instruction that is to be branched to. The assembler calculates the required value of the offset from the PC value of the BLX instruction to this label, then selects an encoding with imm32 set to that offset. Permitted offsets are even numbers in the range –33554432 to 33554430.
	For encoding T1: the label of the instruction that is to be branched to. The assembler calculates the required value of the offset from the PC value of the BL instruction to this label, then selects an encoding with imm32 set to that offset. Permitted offsets are even numbers in the range –16777216 to 16777214.
	For encoding T2: the label of the instruction that is to be branched to. The assembler calculates the required value of the offset from the Align(PC, 4) value of the BLX instruction to this label, then selects an encoding with imm32 set to that offset. Permitted offsets are multiples of 4 in the range –16777216 to 16777212.

Operation

if ConditionPassed() then EncodingSpecificOperations(); if CurrentInstrSet() == InstrSet_A32 then LR = PC32 - 4; else LR = PC32<31:1> : '1'; bits(32) targetAddress; if targetInstrSet == InstrSet_A32 then targetAddress = Align(PC32,4) + imm32; else targetAddress = PC32 + imm32; SelectInstrSet(targetInstrSet); BranchWritePC(targetAddress, BranchType_DIRCALL);

Internal version only: isa v01_31, pseudocode v2024-03_rel ; Build timestamp: 2024-03-25T10:05