CRC32C performs a cyclic redundancy check (CRC) calculation on a value held in a general-purpose register. It takes an input CRC value in the first source operand, performs a CRC on the input value in the second source operand, and returns the output CRC value. The second source operand can be 8, 16, or 32 bits. To align with common usage, the bit order of the values is reversed as part of the operation, and the polynomial 0x1EDC6F41 is used for the CRC calculation.
In an Armv8.0 implementation, this is an optional instruction. From Armv8.1, it is mandatory for all implementations to implement this instruction.
ID_ISAR5.CRC32 indicates whether this instruction is supported in the T32 and A32 instruction sets.
It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| != 1111 | 0 | 0 | 0 | 1 | 0 | sz | 0 | Rn | Rd | (0) | (0) | 1 | (0) | 0 | 1 | 0 | 0 | Rm | |||||||||||||
| cond | C | ||||||||||||||||||||||||||||||
if !IsFeatureImplemented(FEAT_CRC32) then UNDEFINED; constant d = UInt(Rd); constant n = UInt(Rn); constant m = UInt(Rm); constant integer size = 8 << UInt(sz); constant crc32c = (C == '1'); if d == 15 || n == 15 || m == 15 then UNPREDICTABLE; if size == 64 then UNPREDICTABLE; if cond != '1110' then UNPREDICTABLE;
If size == 64, then one of the following behaviors must occur:
If cond != '1110', then one of the following behaviors must occur:
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 1 | 1 | 0 | 1 | Rn | 1 | 1 | 1 | 1 | Rd | 1 | 0 | sz | Rm | ||||||||||
| C | |||||||||||||||||||||||||||||||
if InITBlock() then UNPREDICTABLE; if !IsFeatureImplemented(FEAT_CRC32) then UNDEFINED; constant d = UInt(Rd); constant n = UInt(Rn); constant m = UInt(Rm); constant integer size = 8 << UInt(sz); constant crc32c = (C == '1'); if d == 15 || n == 15 || m == 15 then UNPREDICTABLE; if size == 64 then UNPREDICTABLE;
If size == 64, then one of the following behaviors must occur:
For more information about the constrained unpredictable behavior, see Architectural Constraints on UNPREDICTABLE behaviors.
| <q> |
See Standard assembler syntax fields. A CRC32C instruction must be unconditional. |
| <Rd> |
Is the general-purpose accumulator output register, encoded in the "Rd" field. |
| <Rn> |
Is the general-purpose accumulator input register, encoded in the "Rn" field. |
| <Rm> |
Is the general-purpose data source register, encoded in the "Rm" field. |
if ConditionPassed() then EncodingSpecificOperations(); constant acc = R[n]; // accumulator constant val = R[m]<size-1:0>; // input value constant poly = (if crc32c then 0x1EDC6F41 else 0x04C11DB7)<31:0>; constant tempacc = BitReverse(acc):Zeros(size); constant tempval = BitReverse(val):Zeros(32); // Poly32Mod2 on a bitstring does a polynomial Modulus over {0,1} operation R[d] = BitReverse(Poly32Mod2(tempacc EOR tempval, poly));
If CPSR.DIT is 1 and this instruction passes its condition execution check:
Internal version only: isa v01_31, pseudocode v2024-03_rel ; Build timestamp: 2024-03-25T10:05
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