DMB -- AArch32

DMB

Data Memory Barrier is a memory barrier that ensures the ordering of observations of memory accesses, see Data Memory Barrier (DMB).

It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .

A1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
1	1	1	1	0	1	0	1	0	1	1	1	(1)	(1)	(1)	(1)	(1)	(1)	(1)	(1)	(0)	(0)	(0)	(0)	0	1	0	1	option

A1

DMB{<c>}{<q>} {<option>}

// No additional decoding required

T1

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
1	1	1	1	0	0	1	1	1	0	1	1	(1)	(1)	(1)	(1)	1	0	(0)	0	(1)	(1)	(1)	(1)	0	1	0	1	option

T1

DMB{<c>}{<q>} {<option>}

// No additional decoding required

For more information about the constrained unpredictable behavior, see Architectural Constraints on UNPREDICTABLE behaviors.

Assembler Symbols

<c>	For encoding A1: see Standard assembler syntax fields. Must be AL or omitted.
	For encoding T1: see Standard assembler syntax fields.

<q>	See Standard assembler syntax fields.

<option>

Specifies an optional limitation on the barrier operation. Values are:

SY: Full system is the required shareability domain, reads and writes are the required access types, both before and after the barrier instruction. Can be omitted. This option is referred to as the full system barrier. Encoded as option = 0b1111.
ST: Full system is the required shareability domain, writes are the required access type, both before and after the barrier instruction. SYST is a synonym for ST. Encoded as option = 0b1110.
LD: Full system is the required shareability domain, reads are the required access type before the barrier instruction, and reads and writes are the required access types after the barrier instruction. Encoded as option = 0b1101.
ISH: Inner Shareable is the required shareability domain, reads and writes are the required access types, both before and after the barrier instruction. Encoded as option = 0b1011.
ISHST: Inner Shareable is the required shareability domain, writes are the required access type, both before and after the barrier instruction. Encoded as option = 0b1010.
ISHLD: Inner Shareable is the required shareability domain, reads are the required access type before the barrier instruction, and reads and writes are the required access types after the barrier instruction. Encoded as option = 0b1001.
NSH: Non-shareable is the required shareability domain, reads and writes are the required access, both before and after the barrier instruction. Encoded as option = 0b0111.
NSHST: Non-shareable is the required shareability domain, writes are the required access type both before and after the barrier instruction. Encoded as option = 0b0110.
NSHLD: Non-shareable is the required shareability domain, reads are the required access type before the barrier instruction, and reads and writes are the required access types after the barrier instruction. Encoded as option = 0b0101.
OSH: Outer Shareable is the required shareability domain, reads and writes are the required access types, both before and after the barrier instruction. Encoded as option = 0b0011.
OSHST: Outer Shareable is the required shareability domain, writes are the required access type, both before and after the barrier instruction. Encoded as option = 0b0010.
OSHLD: Outer Shareable is the required shareability domain, reads are the required access type before the barrier instruction, and reads and writes are the required access types after the barrier instruction. Encoded as option = 0b0001.

For more information on whether an access is before or after a barrier instruction, see Data Memory Barrier (DMB). All other encodings of option are reserved. All unsupported and reserved options must execute as a full system DMB operation, but software must not rely on this behavior.

Note

The instruction supports the following alternative <option> values, but Arm recommends that software does not use these alternative values:

SH as an alias for ISH.
SHST as an alias for ISHST.
UN as an alias for NSH.
UNST as an alias for NSHST.

Operation

if ConditionPassed() then EncodingSpecificOperations(); MBReqDomain domain; MBReqTypes types; case option of when '0001' domain = MBReqDomain_OuterShareable; types = MBReqTypes_Reads; when '0010' domain = MBReqDomain_OuterShareable; types = MBReqTypes_Writes; when '0011' domain = MBReqDomain_OuterShareable; types = MBReqTypes_All; when '0101' domain = MBReqDomain_Nonshareable; types = MBReqTypes_Reads; when '0110' domain = MBReqDomain_Nonshareable; types = MBReqTypes_Writes; when '0111' domain = MBReqDomain_Nonshareable; types = MBReqTypes_All; when '1001' domain = MBReqDomain_InnerShareable; types = MBReqTypes_Reads; when '1010' domain = MBReqDomain_InnerShareable; types = MBReqTypes_Writes; when '1011' domain = MBReqDomain_InnerShareable; types = MBReqTypes_All; when '1101' domain = MBReqDomain_FullSystem; types = MBReqTypes_Reads; when '1110' domain = MBReqDomain_FullSystem; types = MBReqTypes_Writes; otherwise domain = MBReqDomain_FullSystem; types = MBReqTypes_All; if PSTATE.EL IN {EL0, EL1} && EL2Enabled() then if HCR.BSU == '11' then domain = MBReqDomain_FullSystem; if HCR.BSU == '10' && domain != MBReqDomain_FullSystem then domain = MBReqDomain_OuterShareable; if HCR.BSU == '01' && domain == MBReqDomain_Nonshareable then domain = MBReqDomain_InnerShareable; DataMemoryBarrier(domain, types);

Internal version only: isa v01_31, pseudocode v2024-03_rel ; Build timestamp: 2024-03-25T10:05

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