Exception Return.
The PE branches to the address held in the register holding the preferred return address, and restores PSTATE from SPSR_<current_mode>.
The register holding the preferred return address is:
The PE checks SPSR_<current_mode> for an illegal return event. See Illegal return events from AArch32 state.
Exception Return is constrained unpredictable in User mode and System mode.
In Debug state, the T1 encoding of ERET executes the DRPS operation.
It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| != 1111 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | (0) | (0) | (0) | (0) | (0) | (0) | (0) | (0) | (0) | (0) | (0) | (0) | 0 | 1 | 1 | 0 | (1) | (1) | (1) | (0) | |||
| cond | |||||||||||||||||||||||||||||||
// No additional decoding required
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 1 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | (0) | 0 | (1) | (1) | (1) | (1) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
if InITBlock() && !LastInITBlock() then UNPREDICTABLE;
For more information about the constrained unpredictable behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors.
if ConditionPassed() then EncodingSpecificOperations(); if !Halted() then if PSTATE.M IN {M32_User,M32_System} then UNPREDICTABLE; // UNDEFINED or NOP else constant new_pc_value = if PSTATE.EL == EL2 then ELR_hyp else R[14]; AArch32.ExceptionReturn(new_pc_value, SPSR_curr[]); else // Perform DRPS operation in Debug state if PSTATE.M == M32_User then UNDEFINED; elsif PSTATE.M == M32_System then UNPREDICTABLE; // UNDEFINED or NOP else SynchronizeContext(); DebugRestorePSR();
If PSTATE.M IN {M32_User,M32_System}, then one of the following behaviors must occur:
Internal version only: isa v01_31, pseudocode v2024-03_rel ; Build timestamp: 2024-03-25T10:05
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