HVC

Hypervisor Call causes a Hypervisor Call exception. For more information, see Hypervisor Call (HVC) exception. Software executing at EL1 can use this instruction to call the hypervisor to request a service.

The HVC instruction is undefined:

The HVC instruction is constrained unpredictable in Hyp mode when EL3 is implemented and using AArch32, and SCR.HCE is set to 0.

On executing an HVC instruction, the HSR, Hyp Syndrome Register reports the exception as a Hypervisor Call exception, using the EC value 0x12, and captures the value of the immediate argument, see Use of the HSR.

It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .

A1

313029282726252423222120191817161514131211109876543210
!= 111100010100imm120111imm4
cond

A1

HVC{<q>} {#}<imm16>

if cond != '1110' then UNPREDICTABLE; constant imm16 = imm12:imm4;

CONSTRAINED UNPREDICTABLE behavior

If cond != '1110', then one of the following behaviors must occur:

T1

15141312111098765432101514131211109876543210
111101111110imm41000imm12

T1

HVC{<q>} {#}<imm16>

constant imm16 = imm4:imm12; if InITBlock() then UNPREDICTABLE;

For more information about the constrained unpredictable behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors.

Assembler Symbols

<q>

See Standard assembler syntax fields. An HVC instruction must be unconditional.

<imm16>

For encoding A1: is a 16-bit unsigned immediate, in the range 0 to 65535, encoded in the "imm12:imm4" field. This value is for assembly and disassembly only. It is reported in the HSR but otherwise is ignored by hardware. An HVC handler might interpret imm16, for example to determine the required service.

For encoding T1: is a 16-bit unsigned immediate, in the range 0 to 65535, encoded in the "imm4:imm12" field. This value is for assembly and disassembly only. It is reported in the HSR but otherwise is ignored by hardware. An HVC handler might interpret imm16, for example to determine the required service.

Operation

EncodingSpecificOperations(); if PSTATE.EL IN {EL0, EL3} || !EL2Enabled() then UNDEFINED; bit hvc_enable; if HaveEL(EL3) then if ELUsingAArch32(EL3) && SCR.HCE == '0' && PSTATE.EL == EL2 then UNPREDICTABLE; else hvc_enable = SCR_curr[].HCE; else hvc_enable = if ELUsingAArch32(EL2) then NOT(HCR.HCD) else NOT(HCR_EL2.HCD); if hvc_enable == '0' then UNDEFINED; else AArch32.CallHypervisor(imm16);

CONSTRAINED UNPREDICTABLE behavior

If ELUsingAArch32(EL3) && SCR.HCE == '0' && PSTATE.EL == EL2, then one of the following behaviors must occur:


Internal version only: isa v01_31, pseudocode v2024-03_rel ; Build timestamp: 2024-03-25T10:05

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