Load-Acquire Exclusive Halfword loads a halfword from memory, zero-extends it to form a 32-bit word, writes it to a register and:
The instruction also has memory ordering semantics as described in Load-Acquire, Store-Release.
For more information about support for shared memory see Synchronization and semaphores. For information about memory accesses see Memory accesses.
It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| != 1111 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | Rn | Rt | (1) | (1) | 1 | 0 | 1 | 0 | 0 | 1 | (1) | (1) | (1) | (1) | |||||||||
| cond | |||||||||||||||||||||||||||||||
constant t = UInt(Rt); constant n = UInt(Rn); if t == 15 || n == 15 then UNPREDICTABLE;
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | Rn | Rt | (1) | (1) | (1) | (1) | 1 | 1 | 0 | 1 | (1) | (1) | (1) | (1) | ||||||
constant t = UInt(Rt); constant n = UInt(Rn); if t == 15 || n == 15 then UNPREDICTABLE;
For more information about the constrained unpredictable behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors.
| <c> |
| <q> |
| <Rt> |
Is the general-purpose register to be transferred, encoded in the "Rt" field. |
| <Rn> |
Is the general-purpose base register, encoded in the "Rn" field. |
if ConditionPassed() then EncodingSpecificOperations(); constant address = R[n]; AArch32.SetExclusiveMonitors(address, 2); R[t] = ZeroExtend(MemO[address, 2], 32);
If CPSR.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.
Internal version only: isa v01_31, pseudocode v2024-03_rel ; Build timestamp: 2024-03-25T10:05
Copyright © 2010-2024 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.