Load data to System register (literal) calculates an address from the PC value and an immediate offset, loads a word from memory, and writes it to the DBGDTRTXint System register. For information about memory accesses, see Memory accesses.
In an implementation that includes EL2, the permitted LDC access to DBGDTRTXint can be trapped to Hyp mode, meaning that an attempt to execute an LDC instruction in a Non-secure mode other than Hyp mode, that would be permitted in the absence of the Hyp trap controls, generates a Hyp Trap exception. For more information, see HDCR.TDA.
For simplicity, the LDC pseudocode does not show this possible trap to Hyp mode.
It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .
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| != 1111 | 1 | 1 | 0 | P | U | 0 | W | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 1 | 1 | 1 | 1 | 0 | imm8 | ||||||||||
| cond | |||||||||||||||||||||||||||||||
LDC{<c>}{<q>} p14, c5, <label>
if P == '0' && U == '0' && W == '0' then UNDEFINED; constant index = (P == '1'); constant add = (U == '1'); constant cp = 14; constant imm32 = ZeroExtend(imm8:'00', 32); if W == '1' || (P == '0' && CurrentInstrSet() != InstrSet_A32) then UNPREDICTABLE;
If W == '1', then one of the following behaviors must occur:
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 1 | 0 | 1 | 1 | 0 | P | U | 0 | W | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 1 | 1 | 1 | 1 | 0 | imm8 | |||||||
if P == '0' && U == '0' && W == '0' then UNDEFINED; constant index = (P == '1'); constant add = (U == '1'); constant cp = 14; constant imm32 = ZeroExtend(imm8:'00', 32); if W == '1' || (P == '0' && CurrentInstrSet() != InstrSet_A32) then UNPREDICTABLE;
If W == '1' || P == '0', then one of the following behaviors must occur:
| <c> |
| <q> |
| <option> |
Is an 8-bit immediate, in the range 0 to 255 enclosed in { }, encoded in the "imm8" field. The value of this field is ignored when executing this instruction. |
| +/- |
Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and
encoded in
|
| <imm> |
Is the immediate offset used for forming the address, a multiple of 4 in the range 0-1020, defaulting to 0 and encoded in the "imm8" field, as <imm>/4. |
The alternative syntax permits the addition or subtraction of the offset and the immediate offset to be specified separately, including permitting a subtraction of 0 that cannot be specified using the normal syntax. For more information, see Use of labels in UAL instruction syntax.
if ConditionPassed() then EncodingSpecificOperations(); constant offset_addr = if add then (Align(PC32,4) + imm32) else (Align(PC32,4) - imm32); constant address = if index then offset_addr else Align(PC32,4); // System register write to DBGDTRTXint. AArch32.SysRegWriteM(cp, ThisInstr(), address);
If CPSR.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.
Internal version only: isa v01_31, pseudocode v2024-03_rel ; Build timestamp: 2024-03-25T10:05
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