LDM (exception return) -- AArch32

LDM (exception return)

Load Multiple (exception return) loads multiple registers from consecutive memory locations using an address from a base register. The SPSR of the current mode is copied to the CPSR. An address adjusted by the size of the data loaded can optionally be written back to the base register.

The registers loaded include the PC. The word loaded for the PC is treated as an address and a branch occurs to that address.

The PE checks the encoding that is copied to the CPSR for an illegal return event. See Illegal return events from AArch32 state.

Load Multiple (exception return) is:

undefined in Hyp mode.
unpredictable in debug state, and in User mode and System mode.

A1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
!= 1111				1	0	0	P	U	1	W	1	Rn				1	register_list
cond

A1

LDM{<amode>}{<c>}{<q>} <Rn>{!}, <registers_with_pc>^

constant n = UInt(Rn); constant registers = register_list; constant wback = (W == '1'); constant increment = (U == '1'); constant wordhigher = (P == U); if n == 15 then UNPREDICTABLE; if wback && registers<n> == '1' then UNPREDICTABLE;

CONSTRAINED UNPREDICTABLE behavior

If wback && registers<n> == '1', then one of the following behaviors must occur:

The instruction is undefined.
The instruction executes as NOP.
The instruction performs all the loads using the specified addressing mode and the content of the register being written back is unknown. In addition, if an exception occurs during the execution of this instruction, the base address might be corrupted so that the instruction cannot be repeated.

For more information about the constrained unpredictable behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors.

Assembler Symbols

<amode>

is one of:

DA: Decrement After. The consecutive memory addresses end at the address in the base register. Encoded as P = 0, U = 0.
FA: Full Ascending. For this instruction, a synonym for DA.
DB: Decrement Before. The consecutive memory addresses end one word below the address in the base register. Encoded as P = 1, U = 0.
EA: Empty Ascending. For this instruction, a synonym for DB.
IA: Increment After. The consecutive memory addresses start at the address in the base register. This is the default. Encoded as P = 0, U = 1.
FD: Full Descending. For this instruction, a synonym for IA.
IB: Increment Before. The consecutive memory addresses start one word above the address in the base register. Encoded as P = 1, U = 1.
ED: Empty Descending. For this instruction, a synonym for IB.

<c>	See Standard assembler syntax fields.

<q>	See Standard assembler syntax fields.

<Rn>	Is the general-purpose base register, encoded in the "Rn" field.

!	The address adjusted by the size of the data loaded is written back to the base register. If specified, it is encoded in the "W" field as 1, otherwise this field defaults to 0.

<registers_with_pc>

Is a list of one or more registers, separated by commas and surrounded by { and }. It specifies the set of registers to be loaded. The registers are loaded with the lowest-numbered register from the lowest memory address, through to the highest-numbered register from the highest memory address. The PC must be specified in the register list, and the instruction causes a branch to the address (data) loaded into the PC. See also Encoding of lists of general-purpose registers and the PC.

Instructions with similar syntax but without the PC included in the registers list are described in LDM (User registers).

Operation

if ConditionPassed() then EncodingSpecificOperations(); if PSTATE.EL == EL2 then UNDEFINED; elsif PSTATE.M IN {M32_User,M32_System} then UNPREDICTABLE; // UNDEFINED or NOP else constant length = 4*BitCount(registers) + 4; address = if increment then R[n] else R[n]-length; if wordhigher then address = address+4; for i = 0 to 14 if registers<i> == '1' then R[i] = MemS[address,4]; address = address + 4; constant new_pc_value = MemS[address,4]; if wback && registers<n> == '0' then R[n] = if increment then R[n]+length else R[n]-length; if wback && registers<n> == '1' then R[n] = bits(32) UNKNOWN; AArch32.ExceptionReturn(new_pc_value, SPSR_curr[]);

CONSTRAINED UNPREDICTABLE behavior

If PSTATE.M IN {M32_User,M32_System}, then one of the following behaviors must occur:

The instruction is undefined.
The instruction executes as NOP.

Operational information

If CPSR.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.

Internal version only: isa v01_31, pseudocode v2024-03_rel ; Build timestamp: 2024-03-25T10:05