Load Register Byte (immediate) calculates an address from a base register value and an immediate offset, loads a byte from memory, zero-extends it to form a 32-bit word, and writes it to a register. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses.
It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 , T2 and T3 ) .
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| != 1111 | 0 | 1 | 0 | P | U | 1 | W | 1 | != 1111 | Rt | imm12 | ||||||||||||||||||||
| cond | Rn | ||||||||||||||||||||||||||||||
if Rn == '1111' then SEE "LDRB (literal)"; if P == '0' && W == '1' then SEE "LDRBT"; constant t = UInt(Rt); constant n = UInt(Rn); constant imm32 = ZeroExtend(imm12, 32); constant index = (P == '1'); constant add = (U == '1'); constant wback = (P == '0') || (W == '1'); if t == 15 || (wback && n == t) then UNPREDICTABLE;
If wback && n == t, then one of the following behaviors must occur:
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 1 | 1 | 1 | 1 | imm5 | Rn | Rt | ||||||||
constant t = UInt(Rt); constant n = UInt(Rn); constant imm32 = ZeroExtend(imm5, 32); constant index = TRUE; constant add = TRUE; constant wback = FALSE;
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | != 1111 | != 1111 | imm12 | |||||||||||||||||
| Rn | Rt | ||||||||||||||||||||||||||||||
if Rt == '1111' then SEE "PLD"; if Rn == '1111' then SEE "LDRB (literal)"; constant t = UInt(Rt); constant n = UInt(Rn); constant imm32 = ZeroExtend(imm12, 32); constant index = TRUE; constant add = TRUE; constant wback = FALSE; // Armv8-A removes UNPREDICTABLE for R13
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | != 1111 | Rt | 1 | P | U | W | imm8 | |||||||||||||
| Rn | |||||||||||||||||||||||||||||||
if Rt == '1111' && P == '1' && U == '0' && W == '0' then SEE "PLD, PLDW (immediate)"; if Rn == '1111' then SEE "LDRB (literal)"; if P == '1' && U == '1' && W == '0' then SEE "LDRBT"; if P == '0' && W == '0' then UNDEFINED; constant t = UInt(Rt); constant n = UInt(Rn); constant imm32 = ZeroExtend(imm8, 32); constant index = (P == '1'); constant add = (U == '1'); constant wback = (W == '1'); if (t == 15 && W == '1') || (wback && n == t) then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13
If wback && n == t, then one of the following behaviors must occur:
For more information about the constrained unpredictable behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors.
| <c> |
| <q> |
| <Rt> |
Is the general-purpose register to be transferred, encoded in the "Rt" field. |
| <Rn> |
For encoding A1, T2 and T3: is the general-purpose base register, encoded in the "Rn" field. For PC use see LDRB (literal). |
|
For encoding T1: is the general-purpose base register, encoded in the "Rn" field. |
| +/- |
Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and
encoded in
|
| + |
Specifies the offset is added to the base register. |
if CurrentInstrSet() == InstrSet_A32 then if ConditionPassed() then EncodingSpecificOperations(); constant offset_addr = if add then (R[n] + imm32) else (R[n] - imm32); constant address = if index then offset_addr else R[n]; R[t] = ZeroExtend(MemU[address,1], 32); if wback then R[n] = offset_addr; else if ConditionPassed() then EncodingSpecificOperations(); constant offset_addr = if add then (R[n] + imm32) else (R[n] - imm32); constant address = if index then offset_addr else R[n]; R[t] = ZeroExtend(MemU[address,1], 32); if wback then R[n] = offset_addr;
If CPSR.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.
Internal version only: isa v01_31, pseudocode v2024-03_rel ; Build timestamp: 2024-03-25T10:05
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