LDRD (immediate)

Load Register Dual (immediate) calculates an address from a base register value and an immediate offset, loads two words from memory, and writes them to two registers. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses.

It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .

A1

if Rn == '1111' then SEE "LDRD (literal)"; if Rt<0> == '1' then UNPREDICTABLE; constant t = UInt(Rt); constant t2 = t+1; constant n = UInt(Rn); constant imm32 = ZeroExtend(imm4H:imm4L, 32); constant index = (P == '1'); constant add = (U == '1'); constant wback = (P == '0') || (W == '1'); if P == '0' && W == '1' then UNPREDICTABLE; if wback && (n == t || n == t2) then UNPREDICTABLE; if t2 == 15 then UNPREDICTABLE;

CONSTRAINED UNPREDICTABLE behavior

If wback && (n == t || n == t2), then one of the following behaviors must occur:

• The instruction is undefined.
• The instruction executes as NOP.
• The instruction performs all of the loads using the specified addressing mode and the content of the register that is written back is unknown. In addition, if an exception occurs during such an instruction, the base address might be corrupted so that the instruction cannot be repeated.

If P == '0' && W == '1', then one of the following behaviors must occur:

• The instruction is undefined.
• The instruction executes as NOP.
• The instruction executes as an LDRD using one of offset, post-indexed, or pre-indexed addressing.

If Rt<0> == '1', then one of the following behaviors must occur:

• The instruction is undefined.
• The instruction executes as NOP.
• The instruction executes with the additional decode: t<0> = '0'.
• The instruction executes with the additional decode: t2 = t.
• The instruction executes as described, with no change to its behavior and no additional side-effects. This does not apply when Rt == '1111'.

T1

if P == '0' && W == '0' then SEE "Related encodings"; if Rn == '1111' then SEE "LDRD (literal)"; constant t = UInt(Rt); constant t2 = UInt(Rt2); constant n = UInt(Rn); constant imm32 = ZeroExtend(imm8:'00', 32); constant index = (P == '1'); constant add = (U == '1'); constant wback = (W == '1'); if wback && (n == t || n == t2) then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13 if t == 15 || t2 == 15 || t == t2 then UNPREDICTABLE;

CONSTRAINED UNPREDICTABLE behavior

If wback && (n == t || n == t2), then one of the following behaviors must occur:

• The instruction is undefined.
• The instruction executes as NOP.
• The instruction performs all of the loads using the specified addressing mode and the content of the register that is written back is unknown. In addition, if an exception occurs during such an instruction, the base address might be corrupted so that the instruction cannot be repeated.

If t == t2, then one of the following behaviors must occur:

• The instruction is undefined.
• The instruction executes as NOP.
• The load instruction executes but the destination register takes an unknown value.

Assembler Symbols