Load Register Dual (literal) calculates an address from the PC value and an immediate offset, loads two words from memory, and writes them to two registers. For information about memory accesses see Memory accesses.
It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| != 1111 | 0 | 0 | 0 | (1) | U | 1 | (0) | 0 | 1 | 1 | 1 | 1 | Rt | imm4H | 1 | 1 | 0 | 1 | imm4L | ||||||||||||
| cond | |||||||||||||||||||||||||||||||
LDRD{<c>}{<q>} <Rt>, <Rt2>, <label> // (Normal form)
LDRD{<c>}{<q>} <Rt>, <Rt2>, [PC, #{+/-}<imm>] // (Alternative form)
if Rt<0> == '1' then UNPREDICTABLE; constant t = UInt(Rt); constant t2 = t+1; constant imm32 = ZeroExtend(imm4H:imm4L, 32); constant add = (U == '1'); if t2 == 15 then UNPREDICTABLE;
If Rt<0> == '1', then one of the following behaviors must occur:
If P == '0' || W == '1', then one of the following behaviors must occur:
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 1 | 0 | 1 | 0 | 0 | P | U | 1 | W | 1 | 1 | 1 | 1 | 1 | Rt | Rt2 | imm8 | |||||||||||||
LDRD{<c>}{<q>} <Rt>, <Rt2>, <label> // (Normal form)
LDRD{<c>}{<q>} <Rt>, <Rt2>, [PC, #{+/-}<imm>] // (Alternative form)
if P == '0' && W == '0' then SEE "Related encodings"; constant t = UInt(Rt); constant t2 = UInt(Rt2); constant imm32 = ZeroExtend(imm8:'00', 32); constant add = (U == '1'); // Armv8-A removes UNPREDICTABLE for R13 if t == 15 || t2 == 15 || t == t2 then UNPREDICTABLE; if W == '1' then UNPREDICTABLE;
If t == t2, then one of the following behaviors must occur:
If W == '1', then one of the following behaviors must occur:
For more information about the constrained unpredictable behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors.
Related encodings: Load/Store dual, Load/Store-Exclusive, Load-Acquire/Store-Release, table branch.
| <c> |
| <q> |
| +/- |
Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and
encoded in
|
The alternative syntax permits the addition or subtraction of the offset and the immediate offset to be specified separately, including permitting a subtraction of 0 that cannot be specified using the normal syntax. For more information, see Use of labels in UAL instruction syntax.
if ConditionPassed() then EncodingSpecificOperations(); constant address = if add then (Align(PC32,4) + imm32) else (Align(PC32,4) - imm32); if IsAligned(address, 8) then constant data = MemA[address,8]; if BigEndian(AccessType_GPR) then R[t] = data<63:32>; R[t2] = data<31:0>; else R[t] = data<31:0>; R[t2] = data<63:32>; else R[t] = MemA[address,4]; R[t2] = MemA[address+4,4];
If CPSR.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.
Internal version only: isa v01_31, pseudocode v2024-03_rel ; Build timestamp: 2024-03-25T10:05
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