LDREXD

Load Register Exclusive Doubleword derives an address from a base register value, loads a 64-bit doubleword from memory, writes it to two registers and:

• If the address has the Shared Memory attribute, marks the physical address as exclusive access for the executing PE in a global monitor.
• Causes the executing PE to indicate an active exclusive access in the local monitor.

For more information about support for shared memory see Synchronization and semaphores. For information about memory accesses see Memory accesses.

It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .

A1

constant t = UInt(Rt); constant t2 = t + 1; constant n = UInt(Rn); if Rt<0> == '1' || t2 == 15 || n == 15 then UNPREDICTABLE;

CONSTRAINED UNPREDICTABLE behavior

If Rt<0> == '1', then one of the following behaviors must occur:

• The instruction is undefined.
• The instruction executes as NOP.
• The instruction executes with the additional decode: t<0> = '0'.
• The instruction executes with the additional decode: t2 = t.
• The instruction executes as described, with no change to its behavior and no additional side effects.

If Rt == '1110', then one of the following behaviors must occur:

• The instruction is undefined.
• The instruction executes as NOP.
• The instruction is handled as described in Using R15.

T1

constant t = UInt(Rt); constant t2 = UInt(Rt2); constant n = UInt(Rn); if t == 15 || t2 == 15 || t == t2 || n == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13

CONSTRAINED UNPREDICTABLE behavior

If t == t2, then one of the following behaviors must occur:

• The instruction is undefined.
• The instruction executes as NOP.
• The load instruction executes but the destination register takes an unknown value.

Assembler Symbols