LDRHT -- AArch32

Load Register Halfword Unprivileged loads a halfword from memory, zero-extends it to form a 32-bit word, and writes it to a register. For information about memory accesses see Memory accesses.

The memory access is restricted as if the PE were running in User mode. This makes no difference if the PE is actually running in User mode.

The T32 instruction uses an offset addressing mode, that calculates the address used for the memory access from a base register value and an immediate offset, and leaves the base register unchanged.

The A32 instruction uses a post-indexed addressing mode, that uses a base register value as the address for the memory access, and calculates a new address from a base register value and an offset and writes it back to the base register. The offset can be an immediate value or a register value.

It has encodings from the following instruction sets: A32 ( A1 and A2 ) and T32 ( T1 ) .

constant t = UInt(Rt); constant n = UInt(Rn); constant postindex = TRUE; constant add = (U == '1'); constant register_form = FALSE; constant imm32 = ZeroExtend(imm4H:imm4L, 32); constant integer m = integer UNKNOWN; if t == 15 || n == 15 || n == t then UNPREDICTABLE;

CONSTRAINED UNPREDICTABLE behavior

constant t = UInt(Rt); constant n = UInt(Rn); constant m = UInt(Rm); constant postindex = TRUE; constant add = (U == '1'); constant register_form = TRUE; constant bits(32) imm32 = bits(32) UNKNOWN; if t == 15 || n == 15 || n == t || m == 15 then UNPREDICTABLE;

CONSTRAINED UNPREDICTABLE behavior

if Rn == '1111' then SEE "LDRH (literal)"; constant t = UInt(Rt); constant n = UInt(Rn); constant postindex = FALSE; constant add = TRUE; constant register_form = FALSE; constant imm32 = ZeroExtend(imm8, 32); constant integer m = integer UNKNOWN; // Armv8-A removes UNPREDICTABLE for R13 if t == 15 then UNPREDICTABLE;

Assembler Symbols

Operation

if ConditionPassed() then EncodingSpecificOperations(); if PSTATE.EL == EL2 then UNPREDICTABLE; // Hyp mode constant offset = if register_form then R[m] else imm32; constant offset_addr = if add then (R[n] + offset) else (R[n] - offset); constant address = if postindex then R[n] else offset_addr; constant data = MemU_unpriv[address,2]; if postindex then R[n] = offset_addr; R[t] = ZeroExtend(data, 32);

CONSTRAINED UNPREDICTABLE behavior

If PSTATE.EL == EL2, then one of the following behaviors must occur:

The instruction is undefined.
The instruction executes as NOP.
The instruction executes as LDRH (immediate).

Operational information

If CPSR.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.

Internal version only: isa v01_31, pseudocode v2024-03_rel ; Build timestamp: 2024-03-25T10:05

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
!= 1111				0	0	0	0	U	1	1	1	Rn				Rt				imm4H				1	0	1	1	imm4L
cond

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
!= 1111				0	0	0	0	U	0	1	1	Rn				Rt				(0)	(0)	(0)	(0)	1	0	1	1	Rm
cond

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
1	1	1	1	1	0	0	0	0	0	1	1	!= 1111				Rt				1	1	1	0	imm8
												Rn

<imm>	For encoding A1: is the 8-bit unsigned immediate byte offset, in the range 0 to 255, defaulting to 0 if omitted, and encoded in the "imm4H:imm4L" field.
	For encoding T1: is an optional 8-bit unsigned immediate byte offset, in the range 0 to 255, defaulting to 0 and encoded in the "imm8" field.