Logical Shift Left, setting flags (immediate) shifts a register value left by an immediate number of bits, shifting in zeros, and writes the result to the destination register.
If the destination register is not the PC, this instruction updates the condition flags based on the result.
The field descriptions for <Rd> identify the encodings where the PC is permitted as the destination register. Arm deprecates any use of these encodings. However, when the destination register is the PC:
This is an alias of MOV, MOVS (register). This means:
It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T2 and T3 ) .
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| != 1111 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 1 | (0) | (0) | (0) | (0) | Rd | != 00000 | 0 | 0 | 0 | Rm | |||||||||||||
| cond | S | imm5 | stype | ||||||||||||||||||||||||||||
LSLS{<c>}{<q>} {<Rd>,} <Rm>, #<imm>
is equivalent to
MOVS{<c>}{<q>} <Rd>, <Rm>, LSL #<imm>
and is always the preferred disassembly.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 0 | 0 | 0 | 0 | != 00000 | Rm | Rd | ||||||||
| op | imm5 | ||||||||||||||
LSLS{<q>} {<Rd>,} <Rm>, #<imm> // (Outside IT block)
is equivalent to
MOVS{<q>} <Rd>, <Rm>, LSL #<imm>
and is the preferred disassembly when !InITBlock().
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | (0) | imm3 | Rd | imm2 | 0 | 0 | Rm | |||||||||
| S | stype | ||||||||||||||||||||||||||||||
LSLS.W {<Rd>,} <Rm>, #<imm> // (Outside IT block, and <Rd>, <Rm>, <imm> can be represented in T2)
LSLS{<c>}{<q>} {<Rd>,} <Rm>, #<imm>
is equivalent to
MOVS{<c>}{<q>} <Rd>, <Rm>, LSL #<imm>
and is always the preferred disassembly.
| <c> |
| <q> |
| <Rd> |
For encoding A1: is the general-purpose destination register, encoded in the "Rd" field. Arm deprecates using the PC as the destination register, but if the PC is used, the instruction performs an exception return, that restores PSTATE from SPSR_<current_mode>. |
|
For encoding T2 and T3: is the general-purpose destination register, encoded in the "Rd" field. |
The description of MOV, MOVS (register) gives the operational pseudocode for this instruction.
Internal version only: isa v01_31, pseudocode v2024-03_rel ; Build timestamp: 2024-03-25T10:05
Copyright © 2010-2024 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.