Move to System register from general-purpose register or execute a System instruction. This instruction copies the value of a general-purpose register to a System register, or executes a System instruction.
The System register and System instruction descriptions identify valid encodings for this instruction. Other encodings are undefined. For more information see About the AArch32 System register interface and General behavior of System registers.
In an implementation that includes EL2, MCR accesses to System registers can be trapped to Hyp mode, meaning that an attempt to execute an MCR instruction in a Non-secure mode other than Hyp mode, that would be permitted in the absence of the Hyp trap controls, generates a Hyp Trap exception. For more information, see EL2 configurable instruction enables, disables, and traps.
Because of the range of possible traps to Hyp mode, the MCR pseudocode does not show these possible traps.
It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| != 1111 | 1 | 1 | 1 | 0 | opc1 | 0 | CRn | Rt | 1 | 1 | 1 | coproc<0> | opc2 | 1 | CRm | ||||||||||||||||
| cond | coproc<3:1> | ||||||||||||||||||||||||||||||
constant t = UInt(Rt); constant cp = if coproc<0> == '0' then 14 else 15; // Armv8-A removes UNPREDICTABLE for R13 if t == 15 then UNPREDICTABLE;
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 1 | 0 | 1 | 1 | 1 | 0 | opc1 | 0 | CRn | Rt | 1 | 1 | 1 | coproc<0> | opc2 | 1 | CRm | |||||||||||||
| coproc<3:1> | |||||||||||||||||||||||||||||||
constant t = UInt(Rt); constant cp = if coproc<0> == '0' then 14 else 15; // Armv8-A removes UNPREDICTABLE for R13 if t == 15 then UNPREDICTABLE;
For more information about the constrained unpredictable behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors.
| <c> |
| <q> |
| <coproc> |
Is the System register encoding space,
encoded in
|
| <opc1> |
Is the opc1 parameter within the System register encoding space, in the range 0 to7, encoded in the "opc1" field. |
| <Rt> |
Is the general-purpose register to be transferred, encoded in the "Rt" field. |
| <CRn> |
Is the CRn parameter within the System register encoding space, in the range c0 to c15, encoded in the "CRn" field. |
| <CRm> |
Is the CRm parameter within the System register encoding space, in the range c0 to c15, encoded in the "CRm" field. |
| <opc2> |
Is the opc2 parameter within the System register encoding space, in the range 0 to7, encoded in the "opc2" field. |
The possible values of { <coproc>, <opc1>, <CRn>, <CRm>, <opc2> } encode the entire System register and System instruction encoding space. Not all of this space is allocated, and the System register and System instruction descriptions identify the allocated encodings.
if ConditionPassed() then EncodingSpecificOperations(); AArch32.SysRegWrite(cp, ThisInstr(), t);
Internal version only: isa v01_31, pseudocode v2024-03_rel ; Build timestamp: 2024-03-25T10:05
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