Multiply Accumulate multiplies two register values, and adds a third register value. The least significant 32 bits of the result are written to the destination register. These 32 bits do not depend on whether the source register values are considered to be signed values or unsigned values.
In an A32 instruction, the condition flags can optionally be updated based on the result. Use of this option adversely affects performance on many implementations.
It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| != 1111 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | S | Rd | Ra | Rm | 1 | 0 | 0 | 1 | Rn | |||||||||||||||
| cond | |||||||||||||||||||||||||||||||
constant d = UInt(Rd); constant n = UInt(Rn); constant m = UInt(Rm); constant a = UInt(Ra); constant setflags = (S == '1'); if d == 15 || n == 15 || m == 15 || a == 15 then UNPREDICTABLE;
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | Rn | != 1111 | Rd | 0 | 0 | 0 | 0 | Rm | ||||||||||||
| Ra | |||||||||||||||||||||||||||||||
if Ra == '1111' then SEE "MUL"; constant d = UInt(Rd); constant n = UInt(Rn); constant m = UInt(Rm); constant a = UInt(Ra); constant setflags = FALSE; // Armv8-A removes UNPREDICTABLE for R13 if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;
For more information about the constrained unpredictable behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors.
| <c> |
| <q> |
| <Rd> |
Is the general-purpose destination register, encoded in the "Rd" field. |
| <Rn> |
Is the first general-purpose source register holding the multiplicand, encoded in the "Rn" field. |
| <Rm> |
Is the second general-purpose source register holding the multiplier, encoded in the "Rm" field. |
| <Ra> |
Is the third general-purpose source register holding the addend, encoded in the "Ra" field. |
if ConditionPassed() then EncodingSpecificOperations(); constant operand1 = SInt(R[n]); // operand1 = UInt(R[n]) produces the same final results constant operand2 = SInt(R[m]); // operand2 = UInt(R[m]) produces the same final results constant addend = SInt(R[a]); // addend = UInt(R[a]) produces the same final results constant result = operand1 * operand2 + addend; R[d] = result<31:0>; if setflags then PSTATE.N = result<31>; PSTATE.Z = IsZeroBit(result<31:0>); // PSTATE.C, PSTATE.V unchanged
If CPSR.DIT is 1, this instruction has passed its condition execution check, and does not use R15 as either its source or destination:
Internal version only: isa v01_31, pseudocode v2024-03_rel ; Build timestamp: 2024-03-25T10:05
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