Move Top writes an immediate value to the top halfword of the destination register. It does not affect the contents of the bottom halfword.
It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| != 1111 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 0 | imm4 | Rd | imm12 | ||||||||||||||||||||
| cond | |||||||||||||||||||||||||||||||
constant d = UInt(Rd); constant imm16 = imm4:imm12; if d == 15 then UNPREDICTABLE;
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 1 | 1 | 0 | i | 1 | 0 | 1 | 1 | 0 | 0 | imm4 | 0 | imm3 | Rd | imm8 | |||||||||||||||
constant d = UInt(Rd); constant imm16 = imm4:i:imm3:imm8; // Armv8-A removes UNPREDICTABLE for R13 if d == 15 then UNPREDICTABLE;
For more information about the constrained unpredictable behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors.
| <c> |
| <q> |
| <Rd> |
Is the general-purpose destination register, encoded in the "Rd" field. |
if ConditionPassed() then EncodingSpecificOperations(); R[d]<31:16> = imm16; // R[d]<15:0> unchanged
If CPSR.DIT is 1, this instruction has passed its condition execution check, and does not use R15 as either its source or destination:
Internal version only: isa v01_31, pseudocode v2024-03_rel ; Build timestamp: 2024-03-25T10:05
Copyright © 2010-2024 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.