MRRC -- AArch32

MRRC

Move to two general-purpose registers from System register. This instruction copies the value of a System register to two general-purpose registers.

The System register descriptions identify valid encodings for this instruction. Other encodings are undefined. For more information see About the AArch32 System register interface and General behavior of System registers.

In an implementation that includes EL2, MRRC accesses to System registers can be trapped to Hyp mode, meaning that an attempt to execute an MRRC instruction in a Non-secure mode other than Hyp mode, that would be permitted in the absence of the Hyp trap controls, generates a Hyp Trap exception. For more information, see EL2 configurable instruction enables, disables, and traps.

Because of the range of possible traps to Hyp mode, the MRRC pseudocode does not show these possible traps.

It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .

A1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
!= 1111				1	1	0	0	0	1	0	1	Rt2				Rt				1	1	1	coproc<0>	opc1				CRm
cond																				coproc<3:1>

A1

MRRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <Rt2>, <CRm>

constant t = UInt(Rt); constant t2 = UInt(Rt2); constant cp = if coproc<0> == '0' then 14 else 15; // Armv8-A removes UNPREDICTABLE for R13 if t == 15 || t2 == 15 || t == t2 then UNPREDICTABLE;

CONSTRAINED UNPREDICTABLE behavior

If t == t2, then one of the following behaviors must occur:

The instruction is undefined.
The instruction executes as NOP.
The value in the destination register is unknown.

T1

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
1	1	1	0	1	1	0	0	0	1	0	1	Rt2				Rt				1	1	1	coproc<0>	opc1				CRm
																				coproc<3:1>

T1

MRRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <Rt2>, <CRm>

constant t = UInt(Rt); constant t2 = UInt(Rt2); constant cp = if coproc<0> == '0' then 14 else 15; // Armv8-A removes UNPREDICTABLE for R13 if t == 15 || t2 == 15 || t == t2 then UNPREDICTABLE;

CONSTRAINED UNPREDICTABLE behavior

If t == t2, then one of the following behaviors must occur:

The instruction is undefined.
The instruction executes as NOP.
The value in the destination register is unknown.

For more information about the constrained unpredictable behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors.

Assembler Symbols

<c>	See Standard assembler syntax fields.

<q>	See Standard assembler syntax fields.

Is the System register encoding space, encoded in coproc<0>:

coproc<0>	<coproc>
0	p14
1	p15

<opc1>

Is the opc1 parameter within the System register encoding space, in the range 0 to 15, encoded in the "opc1" field.

<Rt>	Is the first general-purpose register that is transferred into, encoded in the "Rt" field.

<Rt2>

Is the second general-purpose register that is transferred into, encoded in the "Rt2" field.

<CRm>

Is the CRm parameter within the System register encoding space, in the range c0 to c15, encoded in the "CRm" field.

The possible values of { <coproc>, <opc1>, <CRm> } encode the entire System register encoding space. Not all of this space is allocated, and the System register descriptions identify the allocated encodings.

For the permitted uses of these instructions, as described in this manual, <Rt2> transfers bits[63:32] of the selected System register, while <Rt> transfers bits[31:0].

Operation

if ConditionPassed() then EncodingSpecificOperations(); AArch32.SysRegRead64(cp, ThisInstr(), t, t2);

Internal version only: isa v01_31, pseudocode v2024-03_rel ; Build timestamp: 2024-03-25T10:05