Move Special register to general-purpose register moves the value of the APSR, CPSR, or SPSR_<current_mode> into a general-purpose register.
Arm recommends the APSR form when only the N, Z, C, V, Q, and GE[3:0] bits are being written. For more information, see APSR.
An MRS that accesses the SPSRs is unpredictable if executed in User mode or System mode.
An MRS that is executed in User mode and accesses the CPSR returns an unknown value for the CPSR.{E, A, I, F, M} fields.
It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| != 1111 | 0 | 0 | 0 | 1 | 0 | R | 0 | 0 | (1) | (1) | (1) | (1) | Rd | (0) | (0) | 0 | (0) | 0 | 0 | 0 | 0 | (0) | (0) | (0) | (0) | ||||||
| cond | |||||||||||||||||||||||||||||||
constant d = UInt(Rd); constant read_spsr = (R == '1'); if d == 15 then UNPREDICTABLE;
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 1 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | R | (1) | (1) | (1) | (1) | 1 | 0 | (0) | 0 | Rd | (0) | (0) | 0 | (0) | (0) | (0) | (0) | (0) | |||
constant d = UInt(Rd); constant read_spsr = (R == '1'); // Armv8-A removes UNPREDICTABLE for R13 if d == 15 then UNPREDICTABLE;
For more information about the constrained unpredictable behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors.
| <c> |
| <q> |
| <Rd> |
Is the general-purpose destination register, encoded in the "Rd" field. |
| <spec_reg> |
Is the special register to be accessed,
encoded in
|
if ConditionPassed() then EncodingSpecificOperations(); if read_spsr then if PSTATE.M IN {M32_User,M32_System} then UNPREDICTABLE; else R[d] = SPSR_curr[]; else // CPSR has same bit assignments as SPSR, but with the IT, J, SS, IL, and T bits masked out. constant bits(32) mask = '11111000 11101111 00000011 11011111'; psr_val = GetPSRFromPSTATE(AArch32_NonDebugState, 32) AND mask; if PSTATE.EL == EL0 then // If accessed from User mode return UNKNOWN values for E, A, I, F bits, bits<9:6>, // and for the M field, bits<4:0> psr_val<22> = bits(1) UNKNOWN; psr_val<9:6> = bits(4) UNKNOWN; psr_val<4:0> = bits(5) UNKNOWN; R[d] = psr_val;
If PSTATE.M IN {M32_User, M32_System} && read_spsr, then one of the following behaviors must occur:
Internal version only: isa v01_31, pseudocode v2024-03_rel ; Build timestamp: 2024-03-25T10:05
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