Preload Data (literal) signals the memory system that data memory accesses from a specified address are likely in the near future. The memory system can respond by taking actions that are expected to speed up the memory accesses when they do occur, such as preloading the cache line containing the specified address into the data cache.
The effect of a PLD instruction is implementation defined. For more information, see Preloading caches.
It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | 1 | 1 | 1 | 0 | 1 | 0 | 1 | U | (1) | 0 | 1 | 1 | 1 | 1 | 1 | (1) | (1) | (1) | (1) | imm12 |
constant imm32 = ZeroExtend(imm12, 32); constant add = (U == '1');
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | U | 0 | (0) | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | imm12 |
constant imm32 = ZeroExtend(imm12, 32); constant add = (U == '1');
For more information about the constrained unpredictable behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors.
<c> |
For encoding A1: see Standard assembler syntax fields. Must be AL or omitted. |
For encoding T1: see Standard assembler syntax fields. |
<q> |
+/- |
Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and
encoded in
|
The alternative syntax permits the addition or subtraction of the offset and the immediate offset to be specified separately, including permitting a subtraction of 0 that cannot be specified using the normal syntax. For more information, see Use of labels in UAL instruction syntax.
if ConditionPassed() then EncodingSpecificOperations(); constant address = if add then (Align(PC32,4) + imm32) else (Align(PC32,4) - imm32); Hint_PreloadData(address);
Internal version only: isa v01_31, pseudocode v2024-03_rel ; Build timestamp: 2024-03-25T10:05
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