PLI (immediate, literal) -- AArch32

Preload Instruction signals the memory system that instruction memory accesses from a specified address are likely in the near future. The memory system can respond by taking actions that are expected to speed up the memory accesses when they do occur, such as pre-loading the cache line containing the specified address into the instruction cache.

The effect of a PLI instruction is implementation defined. For more information, see Preloading caches.

It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 , T2 and T3 ) .

A1

PLI{<c>}{<q>} [<Rn> {, #{+/-}<imm>}]

PLI{<c>}{<q>} <label> // (Normal form)

PLI{<c>}{<q>} [PC, #{+/-}<imm>] // (Alternative form)

constant n = UInt(Rn); constant imm32 = ZeroExtend(imm12, 32); constant add = (U == '1');

if Rn == '1111' then SEE "encoding T3"; constant n = UInt(Rn); constant imm32 = ZeroExtend(imm12, 32); constant add = TRUE;

if Rn == '1111' then SEE "encoding T3"; constant n = UInt(Rn); constant imm32 = ZeroExtend(imm8, 32); constant add = FALSE;

T3

PLI{<c>}{<q>} <label> // (Preferred syntax)

PLI{<c>}{<q>} [PC, #{+/-}<imm>] // (Alternative syntax)

constant n = 15; constant imm32 = ZeroExtend(imm12, 32); constant add = (U == '1');

For more information about the constrained unpredictable behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors.

Assembler Symbols

<c>	For encoding A1: see Standard assembler syntax fields. Must be AL or omitted.
	For encoding T1, T2 and T3: see Standard assembler syntax fields.

<q>	See Standard assembler syntax fields.

<label>

The label of the instruction that is likely to be accessed in the near future. The assembler calculates the required value of the offset from the Align(PC, 4) value of the instruction to this label. The offset must be in the range –4095 to 4095.

If the offset is zero or positive, imm32 is equal to the offset and add == TRUE.

If the offset is negative, imm32 is equal to minus the offset and add == FALSE.

<Rn>	Is the general-purpose base register, encoded in the "Rn" field.

+/-

Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and encoded in U:

U	+/-
0	-
1	+

+	Specifies the offset is added to the base register.

<imm>	For encoding A1: is the optional 12-bit unsigned immediate byte offset, in the range 0 to 4095, defaulting to 0 and encoded in the "imm12" field.
	For encoding T1: is an optional 12-bit unsigned immediate byte offset, in the range 0 to 4095, defaulting to 0 and encoded in the "imm12" field.
	For encoding T2: is an 8-bit unsigned immediate byte offset, in the range 0 to 255, defaulting to 0 if omitted, and encoded in the "imm8" field.
	For encoding T3: is a 12-bit unsigned immediate byte offset, in the range 0 to 4095, encoded in the "imm12" field.

For the literal forms of the instruction, encoding T3 is used, or Rn is encoded as 0b1111 in encoding A1, to indicate that the PC is the base register.

The alternative literal syntax permits the addition or subtraction of the offset and the immediate offset to be specified separately, including permitting a subtraction of 0 that cannot be specified using the normal syntax. For more information, see Use of labels in UAL instruction syntax.

Operation

if ConditionPassed() then EncodingSpecificOperations(); constant base = if n == 15 then Align(PC32,4) else R[n]; constant address = if add then (base + imm32) else (base - imm32); Hint_PreloadInstr(address);

Internal version only: isa v01_31, pseudocode v2024-03_rel ; Build timestamp: 2024-03-25T10:05

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
1	1	1	1	0	1	0	0	U	1	0	1	Rn				(1)	(1)	(1)	(1)	imm12

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
1	1	1	1	1	0	0	1	1	0	0	1	!= 1111				1	1	1	1	imm12
												Rn

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
1	1	1	1	1	0	0	1	0	0	0	1	!= 1111				1	1	1	1	1	1	0	0	imm8
												Rn