PUSH -- AArch32

PUSH

Push Multiple Registers to Stack stores multiple general-purpose registers to the stack, storing to consecutive memory locations ending just below the address in SP, and updates SP to point to the start of the stored data.

The lowest-numbered register is stored to the lowest memory address, through to the highest-numbered register to the highest memory address. See also Encoding of lists of general-purpose registers and the PC.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
1	0	1	1	0	1	0	M	register_list

T1

PUSH{<c>}{<q>} <registers> // (Preferred syntax)

STMDB{<c>}{<q>} SP!, <registers> // (Alternate syntax)

constant registers = '0':M:'000000':register_list; constant UnalignedAllowed = FALSE; if BitCount(registers) < 1 then UNPREDICTABLE;

CONSTRAINED UNPREDICTABLE behavior

If BitCount(registers) < 1, then one of the following behaviors must occur:

The instruction is undefined.

The instruction executes as NOP.

The instruction targets an unspecified set of registers. These registers might include R15. If the instruction specifies writeback, the modification to the base address on writeback might differ from the number of registers loaded.

For more information about the constrained unpredictable behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors.

Assembler Symbols

Operation

if ConditionPassed() then EncodingSpecificOperations(); address = R[13] - 4*BitCount(registers); for i = 0 to 14 if registers<i> == '1' then if i == 13 && i != LowestSetBit(registers) then // Only possible for encoding A1 MemA[address,4] = bits(32) UNKNOWN; else if UnalignedAllowed then MemU[address,4] = R[i]; else MemA[address,4] = R[i]; address = address + 4; if registers<15> == '1' then // Only possible for encoding A1 or A2 if UnalignedAllowed then MemU[address,4] = PCStoreValue(); else MemA[address,4] = PCStoreValue(); R[13] = R[13] - 4*BitCount(registers);

Internal version only: isa v01_31, pseudocode v2024-03_rel ; Build timestamp: 2024-03-25T10:05