Reverse Bits reverses the bit order in a 32-bit register.
It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| != 1111 | 0 | 1 | 1 | 0 | 1 | 1 | 1 | 1 | (1) | (1) | (1) | (1) | Rd | (1) | (1) | (1) | (1) | 0 | 0 | 1 | 1 | Rm | |||||||||
| cond | |||||||||||||||||||||||||||||||
constant d = UInt(Rd); constant m = UInt(Rm); if d == 15 || m == 15 then UNPREDICTABLE;
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 1 | Rn | 1 | 1 | 1 | 1 | Rd | 1 | 0 | 1 | 0 | Rm | |||||||||
constant d = UInt(Rd); constant m = UInt(Rm); constant n = UInt(Rn); // Armv8-A removes UNPREDICTABLE for R13 if m != n || d == 15 || m == 15 then UNPREDICTABLE;
If m != n, then one of the following behaviors must occur:
For more information about the constrained unpredictable behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors.
| <c> |
| <q> |
| <Rd> |
Is the general-purpose destination register, encoded in the "Rd" field. |
if ConditionPassed() then EncodingSpecificOperations(); bits(32) result; for i = 0 to 31 result<31-i> = R[m]<i>; R[d] = result;
If CPSR.DIT is 1, this instruction has passed its condition execution check, and does not use R15 as either its source or destination:
Internal version only: isa v01_31, pseudocode v2024-03_rel ; Build timestamp: 2024-03-25T10:05
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