Return From Exception loads two consecutive memory locations using an address in a base register:
An address adjusted by the size of the data loaded can optionally be written back to the base register.
The PE checks the value of the word loaded from the higher address for an illegal return event. See Illegal return events from AArch32 state.
RFE is undefined in Hyp mode and constrained unpredictable in User mode.
It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 and T2 ) .
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 1 | 1 | 1 | 0 | 0 | P | U | 0 | W | 1 | Rn | (0) | (0) | (0) | (0) | (1) | (0) | (1) | (0) | (0) | (0) | (0) | (0) | (0) | (0) | (0) | (0) | |||
RFEDA{<c>}{<q>} <Rn>{!} // (Preferred syntax)
RFEFA{<c>}{<q>} <Rn>{!} // (Alternate syntax, Full Ascending stack)
RFEDB{<c>}{<q>} <Rn>{!} // (Preferred syntax)
RFEEA{<c>}{<q>} <Rn>{!} // (Alternate syntax, Empty Ascending stack)
RFE{IA}{<c>}{<q>} <Rn>{!} // (Preferred syntax)
RFEFD{<c>}{<q>} <Rn>{!} // (Alternate syntax, Full Descending stack)
RFEIB{<c>}{<q>} <Rn>{!} // (Preferred syntax)
RFEED{<c>}{<q>} <Rn>{!} // (Alternate syntax, Empty Descending stack)
constant n = UInt(Rn); constant wback = (W == '1'); constant increment = (U == '1'); constant wordhigher = (P == U); if n == 15 then UNPREDICTABLE;
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | W | 1 | Rn | (1) | (1) | (0) | (0) | (0) | (0) | (0) | (0) | (0) | (0) | (0) | (0) | (0) | (0) | (0) | (0) | |||
RFEDB{<c>}{<q>} <Rn>{!} // (Outside or last in IT block, preferred syntax)
RFEFA{<c>}{<q>} <Rn>{!} // (Outside or last in IT block, alternate syntax, Full Ascending stack)
constant n = UInt(Rn); constant wback = (W == '1'); constant increment = FALSE; constant wordhigher = FALSE; if n == 15 then UNPREDICTABLE; if InITBlock() && !LastInITBlock() then UNPREDICTABLE;
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 1 | 0 | 1 | 0 | 0 | 1 | 1 | 0 | W | 1 | Rn | (1) | (1) | (0) | (0) | (0) | (0) | (0) | (0) | (0) | (0) | (0) | (0) | (0) | (0) | (0) | (0) | |||
RFE{IA}{<c>}{<q>} <Rn>{!} // (Outside or last in IT block, preferred syntax)
RFEFD{<c>}{<q>} <Rn>{!} // (Outside or last in IT block, alternate syntax, Full Descending stack)
constant n = UInt(Rn); constant wback = (W == '1'); constant increment = TRUE; constant wordhigher = FALSE; if n == 15 then UNPREDICTABLE; if InITBlock() && !LastInITBlock() then UNPREDICTABLE;
For more information about the constrained unpredictable behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors.
| IA |
For encoding A1: is an optional suffix to indicate the Increment After variant. |
|
For encoding T2: is an optional suffix for the Increment After form. |
| <c> |
For encoding A1: see Standard assembler syntax fields. <c> must be AL or omitted. |
|
For encoding T1 and T2: see Standard assembler syntax fields. |
| <q> |
| <Rn> |
Is the general-purpose base register, encoded in the "Rn" field. |
| ! |
The address adjusted by the size of the data loaded is written back to the base register. If specified, it is encoded in the "W" field as 1, otherwise this field defaults to 0. |
RFEFA, RFEEA, RFEFD, and RFEED are pseudo-instructions for RFEDA, RFEDB, RFEIA, and RFEIB respectively, referring to their use for popping data from Full Ascending, Empty Ascending, Full Descending, and Empty Descending stacks.
if ConditionPassed() then EncodingSpecificOperations(); if PSTATE.EL == EL2 then UNDEFINED; elsif PSTATE.EL == EL0 then UNPREDICTABLE; // UNDEFINED or NOP else address = if increment then R[n] else R[n]-8; if wordhigher then address = address+4; constant new_pc_value = MemA[address,4]; constant spsr = MemA[address+4,4]; if wback then R[n] = if increment then R[n]+8 else R[n]-8; AArch32.ExceptionReturn(new_pc_value, spsr);
If PSTATE.EL == EL0, then one of the following behaviors must occur:
Internal version only: isa v01_31, pseudocode v2024-03_rel ; Build timestamp: 2024-03-25T10:05
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