Rotate Right, setting flags (immediate) provides the value of the contents of a register rotated by a constant value. The bits that are rotated off the right end are inserted into the vacated bit positions on the left.
If the destination register is not the PC, this instruction updates the condition flags based on the result.
The field descriptions for <Rd> identify the encodings where the PC is permitted as the destination register. Arm deprecates any use of these encodings. However, when the destination register is the PC:
This is an alias of MOV, MOVS (register). This means:
It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T3 ) .
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| != 1111 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 1 | (0) | (0) | (0) | (0) | Rd | != 00000 | 1 | 1 | 0 | Rm | |||||||||||||
| cond | S | imm5 | stype | ||||||||||||||||||||||||||||
RORS{<c>}{<q>} {<Rd>,} <Rm>, #<imm>
is equivalent to
MOVS{<c>}{<q>} <Rd>, <Rm>, ROR #<imm>
and is always the preferred disassembly.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | (0) | imm3 | Rd | imm2 | 1 | 1 | Rm | |||||||||
| S | stype | ||||||||||||||||||||||||||||||
RORS{<c>}{<q>} {<Rd>,} <Rm>, #<imm>
is equivalent to
MOVS{<c>}{<q>} <Rd>, <Rm>, ROR #<imm>
and is always the preferred disassembly.
| <c> |
| <q> |
| <Rd> |
For encoding A1: is the general-purpose destination register, encoded in the "Rd" field. Arm deprecates using the PC as the destination register, but if the PC is used, the instruction performs an exception return, that restores PSTATE from SPSR_<current_mode>. |
|
For encoding T3: is the general-purpose destination register, encoded in the "Rd" field. |
| <imm> |
For encoding A1: is the shift amount, in the range 1 to 31, encoded in the "imm5" field. |
|
For encoding T3: is the shift amount, in the range 1 to 31, encoded in the "imm3:imm2" field. |
The description of MOV, MOVS (register) gives the operational pseudocode for this instruction.
Internal version only: isa v01_31, pseudocode v2024-03_rel ; Build timestamp: 2024-03-25T10:05
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