RSB, RSBS (register)

Reverse Subtract (register) subtracts a register value from an optionally-shifted register value, and writes the result to the destination register.

If the destination register is not the PC, the RSBS variant of the instruction updates the condition flags based on the result.

The field descriptions for <Rd> identify the encodings where the PC is permitted as the destination register. ARM deprecates any use of these encodings. However, when the destination register is the PC:

• The RSB variant of the instruction is an interworking branch, see Pseudocode description of operations on the AArch32 general-purpose registers and the PC.
• The RSBS variant of the instruction performs an exception return without the use of the stack. In this case:
  • The PE branches to the address written to the PC, and restores PSTATE from SPSR_<current_mode>.
  • The PE checks SPSR_<current_mode> for an illegal return event. See Illegal return events from AArch32 state.
  • The instruction is undefined in Hyp mode.
  • The instruction is constrained unpredictable in User mode and System mode.

It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .

A1

constant d = UInt(Rd); constant n = UInt(Rn); constant m = UInt(Rm); constant setflags = (S == '1'); constant (shift_t, shift_n) = DecodeImmShift(stype, imm5);

T1

constant d = UInt(Rd); constant n = UInt(Rn); constant m = UInt(Rm); constant setflags = (S == '1'); constant (shift_t, shift_n) = DecodeImmShift(stype, imm3:imm2); // Armv8-A removes UNPREDICTABLE for R13 if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;

Assembler Symbols