Secure Monitor Call causes a Secure Monitor Call exception. For more information, see Secure Monitor Call (SMC) exception.
SMC is available only for software executing at EL1 or higher. It is undefined in User mode.
If the values of HCR.TSC and SCR.SCD are both 0, execution of an SMC instruction at EL1 or higher generates a Secure Monitor Call exception that is taken to EL3. When EL3 is using AArch32 this exception is taken to Monitor mode. When EL3 is using AArch64, it is the SCR_EL3.SMD bit, rather than the SCR.SCD bit, that can change the effect of executing an SMC instruction.
If the value of HCR.TSC is 1, execution of an SMC instruction in a Non-secure EL1 mode generates an exception that is taken to EL2, regardless of the value of SCR.SCD. When EL2 is using AArch32, this is a Hyp Trap exception that is taken to Hyp mode. For more information, see HCR.TSC.
If the value of HCR.TSC is 0 and the value of SCR.SCD is 1, the SMC instruction is:
It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| != 1111 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | (0) | (0) | (0) | (0) | (0) | (0) | (0) | (0) | (0) | (0) | (0) | (0) | 0 | 1 | 1 | 1 | imm4 | ||||||
| cond | |||||||||||||||||||||||||||||||
// imm4 is for assembly/disassembly only and is ignored by hardware
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | imm4 | 1 | 0 | 0 | 0 | (0) | (0) | (0) | (0) | (0) | (0) | (0) | (0) | (0) | (0) | (0) | (0) | |||
// imm4 is for assembly/disassembly only and is ignored by hardware if InITBlock() && !LastInITBlock() then UNPREDICTABLE;
For more information about the constrained unpredictable behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors.
| <c> |
| <q> |
if ConditionPassed() then EncodingSpecificOperations(); AArch32.CheckForSMCUndefOrTrap(); if !ELUsingAArch32(EL3) then if SCR_EL3.SMD == '1' then // SMC disabled. UNDEFINED; else if SCR.SCD == '1' then // SMC disabled if CurrentSecurityState() == SS_Secure then // Executes either as a NOP or UNALLOCATED. constant c = ConstrainUnpredictable(Unpredictable_SMD); assert c IN {Constraint_NOP, Constraint_UNDEF}; if c == Constraint_NOP then EndOfInstruction(); UNDEFINED; if !ELUsingAArch32(EL3) then AArch64.CallSecureMonitor(Zeros(16)); else AArch32.TakeSMCException();
If SCR.SCD == '1' && CurrentSecurityState() == SS_Secure, then one of the following behaviors must occur:
Internal version only: isa v01_31, pseudocode v2024-03_rel ; Build timestamp: 2024-03-25T10:05
Copyright © 2010-2024 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.