SMLALBB, SMLALBT, SMLALTB, SMLALTT

Signed Multiply Accumulate Long (halfwords) multiplies two signed 16-bit values to produce a 32-bit value, and accumulates this with a 64-bit value. The multiply acts on two signed 16-bit quantities, taken from either the bottom or the top half of their respective source registers. The other halves of these source registers are ignored. The 32-bit product is sign-extended and accumulated with a 64-bit accumulate value.

Overflow is possible during this instruction, but only as a result of the 64-bit addition. This overflow is not detected if it occurs. Instead, the result wraps around modulo 2⁶⁴.

It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .

A1

constant dLo = UInt(RdLo); constant dHi = UInt(RdHi); constant n = UInt(Rn); constant m = UInt(Rm); constant n_high = (N == '1'); constant m_high = (M == '1'); if dLo == 15 || dHi == 15 || n == 15 || m == 15 then UNPREDICTABLE; if dHi == dLo then UNPREDICTABLE;

CONSTRAINED UNPREDICTABLE behavior

If dHi == dLo, then one of the following behaviors must occur:

• The instruction is undefined.
• The instruction executes as NOP.
• The value in the destination register is unknown.

T1

constant dLo = UInt(RdLo); constant dHi = UInt(RdHi); constant n = UInt(Rn); constant m = UInt(Rm); constant n_high = (N == '1'); constant m_high = (M == '1'); if dLo == 15 || dHi == 15 || n == 15 || m == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13 if dHi == dLo then UNPREDICTABLE;

CONSTRAINED UNPREDICTABLE behavior

If dHi == dLo, then one of the following behaviors must occur:

• The instruction is undefined.
• The instruction executes as NOP.
• The value in the destination register is unknown.

Assembler Symbols