Signed Multiply Accumulate Long Dual performs two signed 16 x 16-bit multiplications. It adds the products to a 64-bit accumulate operand.
Optionally, the instruction can exchange the halfwords of the second operand before performing the arithmetic. This produces top x bottom and bottom x top multiplication.
Overflow is possible during this instruction, but only as a result of the 64-bit addition. This overflow is not detected if it occurs. Instead, the result wraps around modulo 264.
It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| != 1111 | 0 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | RdHi | RdLo | Rm | 0 | 0 | M | 1 | Rn | |||||||||||||||
| cond | |||||||||||||||||||||||||||||||
constant dLo = UInt(RdLo); constant dHi = UInt(RdHi); constant n = UInt(Rn); constant m = UInt(Rm); constant m_swap = (M == '1'); if dLo == 15 || dHi == 15 || n == 15 || m == 15 then UNPREDICTABLE; if dHi == dLo then UNPREDICTABLE;
If dHi == dLo, then one of the following behaviors must occur:
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | Rn | RdLo | RdHi | 1 | 1 | 0 | M | Rm | ||||||||||||
constant dLo = UInt(RdLo); constant dHi = UInt(RdHi); constant n = UInt(Rn); constant m = UInt(Rm); constant m_swap = (M == '1'); if dLo == 15 || dHi == 15 || n == 15 || m == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13 if dHi == dLo then UNPREDICTABLE;
If dHi == dLo, then one of the following behaviors must occur:
For more information about the constrained unpredictable behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors.
| <c> |
| <q> |
| <RdLo> |
Is the general-purpose source register holding the lower 32 bits of the addend, and the destination register for the lower 32 bits of the result, encoded in the "RdLo" field. |
| <RdHi> |
Is the general-purpose source register holding the upper 32 bits of the addend, and the destination register for the upper 32 bits of the result, encoded in the "RdHi" field. |
| <Rn> |
Is the first general-purpose source register, encoded in the "Rn" field. |
| <Rm> |
Is the second general-purpose source register, encoded in the "Rm" field. |
if ConditionPassed() then EncodingSpecificOperations(); constant operand2 = if m_swap then ROR(R[m],16) else R[m]; constant product1 = SInt(R[n]<15:0>) * SInt(operand2<15:0>); constant product2 = SInt(R[n]<31:16>) * SInt(operand2<31:16>); constant result = product1 + product2 + SInt(R[dHi]:R[dLo]); R[dHi] = result<63:32>; R[dLo] = result<31:0>;
If CPSR.DIT is 1, this instruction has passed its condition execution check, and does not use R15 as either its source or destination:
Internal version only: isa v01_31, pseudocode v2024-03_rel ; Build timestamp: 2024-03-25T10:05
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