Signed Multiply Accumulate (word by halfword) performs a signed multiply accumulate operation. The multiply acts on a signed 32-bit quantity and a signed 16-bit quantity. The signed 16-bit quantity is taken from either the bottom or the top half of its source register. The other half of the second source register is ignored. The top 32 bits of the 48-bit product are added to a 32-bit accumulate value and the result is written to the destination register. The bottom 16 bits of the 48-bit product are ignored.
If overflow occurs during the addition of the accumulate value, the instruction sets PSTATE.Q to 1. No overflow can occur during the multiplication.
It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| != 1111 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | Rd | Ra | Rm | 1 | M | 0 | 0 | Rn | |||||||||||||||
| cond | |||||||||||||||||||||||||||||||
constant d = UInt(Rd); constant n = UInt(Rn); constant m = UInt(Rm); constant a = UInt(Ra); constant m_high = (M == '1'); if d == 15 || n == 15 || m == 15 || a == 15 then UNPREDICTABLE;
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 0 | 0 | 1 | 1 | Rn | != 1111 | Rd | 0 | 0 | 0 | M | Rm | ||||||||||||
| Ra | |||||||||||||||||||||||||||||||
if Ra == '1111' then SEE "SMULWB, SMULWT"; constant d = UInt(Rd); constant n = UInt(Rn); constant m = UInt(Rm); constant a = UInt(Ra); constant m_high = (M == '1'); // Armv8-A removes UNPREDICTABLE for R13 if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;
For more information about the constrained unpredictable behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors.
| <c> |
| <q> |
| <Rd> |
Is the general-purpose destination register, encoded in the "Rd" field. |
| <Rn> |
Is the first general-purpose source register holding the multiplicand, encoded in the "Rn" field. |
| <Rm> |
Is the second general-purpose source register holding the multiplier in the bottom or top half (selected by <y>), encoded in the "Rm" field. |
| <Ra> |
Is the third general-purpose source register holding the addend, encoded in the "Ra" field. |
if ConditionPassed() then EncodingSpecificOperations(); constant operand2 = if m_high then R[m]<31:16> else R[m]<15:0>; constant result = SInt(R[n]) * SInt(operand2) + (SInt(R[a]) << 16); R[d] = result<47:16>; if (result >> 16) != SInt(R[d]) then // Signed overflow PSTATE.Q = '1';
If CPSR.DIT is 1, this instruction has passed its condition execution check, and does not use R15 as either its source or destination:
Internal version only: isa v01_31, pseudocode v2024-03_rel ; Build timestamp: 2024-03-25T10:05
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