Store Return State stores the LR_<current_mode> and SPSR_<current_mode> to the stack of a specified mode. For information about memory accesses see Memory accesses.
SRS is undefined in Hyp mode.
SRS is constrained unpredictable if it is executed in User or System mode, or if the specified mode is any of the following:
If EL3 is using AArch64 and an SRS instruction that is executed in a Secure EL1 mode specifies Monitor mode, it is trapped to EL3.
It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 and T2 ) .
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 1 | 1 | 1 | 0 | 0 | P | U | 1 | W | 0 | (1) | (1) | (0) | (1) | (0) | (0) | (0) | (0) | (0) | (1) | (0) | (1) | (0) | (0) | (0) | mode | ||||
constant wback = (W == '1'); constant increment = (U == '1'); constant wordhigher = (P == U);
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | W | 0 | (1) | (1) | (0) | (1) | (1) | (1) | (0) | (0) | (0) | (0) | (0) | (0) | (0) | (0) | (0) | mode | ||||
constant wback = (W == '1'); constant increment = FALSE; constant wordhigher = FALSE;
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 1 | 0 | 1 | 0 | 0 | 1 | 1 | 0 | W | 0 | (1) | (1) | (0) | (1) | (1) | (1) | (0) | (0) | (0) | (0) | (0) | (0) | (0) | (0) | (0) | mode | ||||
constant wback = (W == '1'); constant increment = TRUE; constant wordhigher = FALSE;
For more information about the constrained unpredictable behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors, and particularly SRS (T32) and SRS (A32).
| IA |
For encoding A1: is an optional suffix to indicate the Increment After variant. |
|
For encoding T2: is an optional suffix for the Increment After form. |
| <c> |
For encoding A1: see Standard assembler syntax fields. <c> must be AL or omitted. |
|
For encoding T1 and T2: see Standard assembler syntax fields. |
| <q> |
| ! |
The address adjusted by the size of the data loaded is written back to the base register. If specified, it is encoded in the "W" field as 1, otherwise this field defaults to 0. |
| <mode> |
Is the number of the mode whose Banked SP is used as the base register, encoded in the "mode" field. For details of PE modes and their numbers see AArch32 PE mode descriptions. |
SRSFA, SRSEA, SRSFD, and SRSED are pseudo-instructions for SRSIB, SRSIA, SRSDB, and SRSDA respectively, referring to their use for pushing data onto Full Ascending, Empty Ascending, Full Descending, and Empty Descending stacks.
if CurrentInstrSet() == InstrSet_A32 then if ConditionPassed() then EncodingSpecificOperations(); if PSTATE.EL == EL2 then // UNDEFINED at EL2 UNDEFINED; // Check for UNPREDICTABLE cases. The definition of UNPREDICTABLE does not permit these // to be security holes if PSTATE.M IN {M32_User,M32_System} then UNPREDICTABLE; elsif mode == M32_Hyp then // Check for attempt to access Hyp mode SP UNPREDICTABLE; elsif mode == M32_Monitor then // Check for attempt to access Monitor mode SP if !HaveEL(EL3) || CurrentSecurityState() != SS_Secure then UNPREDICTABLE; elsif !ELUsingAArch32(EL3) then AArch64.MonitorModeTrap(); elsif BadMode(mode) then UNPREDICTABLE; constant base = Rmode[13,mode]; address = if increment then base else base-8; if wordhigher then address = address+4; MemA[address,4] = LR; MemA[address+4,4] = SPSR_curr[]; if wback then Rmode[13,mode] = if increment then base+8 else base-8; else if ConditionPassed() then EncodingSpecificOperations(); if PSTATE.EL == EL2 then // UNDEFINED at EL2 UNDEFINED; // Check for UNPREDICTABLE cases. The definition of UNPREDICTABLE does not permit these // to be security holes if PSTATE.M IN {M32_User,M32_System} then UNPREDICTABLE; elsif mode == M32_Hyp then // Check for attempt to access Hyp mode SP UNPREDICTABLE; elsif mode == M32_Monitor then // Check for attempt to access Monitor mode SP if !HaveEL(EL3) || CurrentSecurityState() != SS_Secure then UNPREDICTABLE; elsif !ELUsingAArch32(EL3) then AArch64.MonitorModeTrap(); elsif BadMode(mode) then UNPREDICTABLE; constant base = Rmode[13,mode]; address = if increment then base else base-8; if wordhigher then address = address+4; MemA[address,4] = LR; MemA[address+4,4] = SPSR_curr[]; if wback then Rmode[13,mode] = if increment then base+8 else base-8;
If PSTATE.M IN {M32_User,M32_System}, then one of the following behaviors must occur:
If mode == M32_Hyp, then one of the following behaviors must occur:
If mode == M32_Monitor && (!HaveEL(EL3) || CurrentSecurityState() != SS_Secure), then one of the following behaviors must occur:
If BadMode(mode), then one of the following behaviors must occur:
Internal version only: isa v01_31, pseudocode v2024-03_rel ; Build timestamp: 2024-03-25T10:05
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