Signed Saturate 16 saturates two signed 16-bit values to a selected signed range.
This instruction sets PSTATE.Q to 1 if the operation saturates.
It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
!= 1111 | 0 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | sat_imm | Rd | (1) | (1) | (1) | (1) | 0 | 0 | 1 | 1 | Rn | ||||||||||||
cond |
constant d = UInt(Rd); constant n = UInt(Rn); constant saturate_to = UInt(sat_imm)+1; if d == 15 || n == 15 then UNPREDICTABLE;
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | 1 | 1 | 1 | 0 | (0) | 1 | 1 | 0 | 0 | 1 | 0 | Rn | 0 | 0 | 0 | 0 | Rd | 0 | 0 | (0) | (0) | sat_imm |
constant d = UInt(Rd); constant n = UInt(Rn); constant saturate_to = UInt(sat_imm)+1; // Armv8-A removes UNPREDICTABLE for R13 if d == 15 || n == 15 then UNPREDICTABLE;
For more information about the constrained unpredictable behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors.
<c> |
<q> |
<Rd> |
Is the general-purpose destination register, encoded in the "Rd" field. |
<imm> |
Is the bit position for saturation, in the range 1 to 16, encoded in the "sat_imm" field as <imm>-1. |
<Rn> |
Is the general-purpose source register, encoded in the "Rn" field. |
if ConditionPassed() then EncodingSpecificOperations(); constant (result1, sat1) = SignedSatQ(SInt(R[n]<15:0>), saturate_to); constant (result2, sat2) = SignedSatQ(SInt(R[n]<31:16>), saturate_to); R[d]<15:0> = SignExtend(result1, 16); R[d]<31:16> = SignExtend(result2, 16); if sat1 || sat2 then PSTATE.Q = '1';
Internal version only: isa v01_31, pseudocode v2024-03_rel ; Build timestamp: 2024-03-25T10:05
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