Base Instructions
SIMD&FP Instructions
A32 Instructions by Encoding
T32 Instructions by Encoding
Shared Pseudocode
Proprietary Notice

STR (immediate)

Store Register (immediate) calculates an address from a base register value and an immediate offset, and stores a word from a register to memory. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses.

This instruction is used by the alias PUSH (single register).

It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 , T2 , T3 and T4 ) .

A1

313029282726252423222120191817161514131211109876543210
!= 1111010PU0W0RnRtimm12
cond

Offset (P == 1 && W == 0)

STR{<c>}{<q>} <Rt>, [<Rn> {, #{+/-}<imm>}]

Post-indexed (P == 0 && W == 0)

STR{<c>}{<q>} <Rt>, [<Rn>], #{+/-}<imm>

Pre-indexed (P == 1 && W == 1)

STR{<c>}{<q>} <Rt>, [<Rn>, #{+/-}<imm>]!

if P == '0' && W == '1' then SEE "STRT"; constant t = UInt(Rt); constant n = UInt(Rn); constant imm32 = ZeroExtend(imm12, 32); constant index = (P == '1'); constant add = (U == '1'); constant wback = (P == '0') || (W == '1'); if wback && (n == 15 || n == t) then UNPREDICTABLE;

CONSTRAINED UNPREDICTABLE behavior

If wback && n == t, then one of the following behaviors must occur:

If wback && n == 15, then one of the following behaviors must occur:

T1

1514131211109876543210
01100imm5RnRt

T1

STR{<c>}{<q>} <Rt>, [<Rn> {, #{+}<imm>}]

constant t = UInt(Rt); constant n = UInt(Rn); constant imm32 = ZeroExtend(imm5:'00', 32); constant index = TRUE; constant add = TRUE; constant wback = FALSE;

T2

1514131211109876543210
10010Rtimm8

T2

STR{<c>}{<q>} <Rt>, [SP{, #{+}<imm>}]

constant t = UInt(Rt); constant n = 13; constant imm32 = ZeroExtend(imm8:'00', 32); constant index = TRUE; constant add = TRUE; constant wback = FALSE;

T3

15141312111098765432101514131211109876543210
111110001100!= 1111Rtimm12
Rn

T3

STR{<c>}.W <Rt>, [<Rn> {, #{+}<imm>}] // (<Rt>, <Rn>, <imm> can be represented in T1 or T2)

STR{<c>}{<q>} <Rt>, [<Rn> {, #{+}<imm>}]

if Rn == '1111' then UNDEFINED; constant t = UInt(Rt); constant n = UInt(Rn); constant imm32 = ZeroExtend(imm12, 32); constant index = TRUE; constant add = TRUE; constant wback = FALSE; if t == 15 then UNPREDICTABLE;

CONSTRAINED UNPREDICTABLE behavior

If t == 15, then one of the following behaviors must occur:

T4

15141312111098765432101514131211109876543210
111110000100!= 1111Rt1PUWimm8
Rn

Offset (P == 1 && U == 0 && W == 0)

STR{<c>}{<q>} <Rt>, [<Rn> {, #-<imm>}]

Post-indexed (P == 0 && W == 1)

STR{<c>}{<q>} <Rt>, [<Rn>], #{+/-}<imm>

Pre-indexed (P == 1 && W == 1)

STR{<c>}{<q>} <Rt>, [<Rn>, #{+/-}<imm>]!

if P == '1' && U == '1' && W == '0' then SEE "STRT"; if Rn == '1111' || (P == '0' && W == '0') then UNDEFINED; constant t = UInt(Rt); constant n = UInt(Rn); constant imm32 = ZeroExtend(imm8, 32); constant index = (P == '1'); constant add = (U == '1'); constant wback = (W == '1'); if t == 15 || (wback && n == t) then UNPREDICTABLE;

CONSTRAINED UNPREDICTABLE behavior

If wback && n == t, then one of the following behaviors must occur:

If t == 15, then one of the following behaviors must occur:

For more information about the constrained unpredictable behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors.

Assembler Symbols

<c>

See Standard assembler syntax fields.

<q>

See Standard assembler syntax fields.

<Rt>

For encoding A1: is the general-purpose register to be transferred, encoded in the "Rt" field. The PC can be used, but this is deprecated.

For encoding T1, T2, T3 and T4: is the general-purpose register to be transferred, encoded in the "Rt" field.

<Rn>

For encoding A1: is the general-purpose base register, encoded in the "Rn" field. The PC can be used in the offset variant, but this is deprecated.

For encoding T1, T3 and T4: is the general-purpose base register, encoded in the "Rn" field.

+/-

Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and encoded in U:

U +/-
0 -
1 +
+

Specifies the offset is added to the base register.

<imm>

For encoding A1: is the 12-bit unsigned immediate byte offset, in the range 0 to 4095, defaulting to 0 if omitted, and encoded in the "imm12" field.

For encoding T1: is the optional positive unsigned immediate byte offset, a multiple of 4, in the range 0 to 124, defaulting to 0 and encoded in the "imm5" field as <imm>/4.

For encoding T2: is the optional positive unsigned immediate byte offset, a multiple of 4, in the range 0 to 1020, defaulting to 0 and encoded in the "imm8" field as <imm>/4.

For encoding T3: is an optional 12-bit unsigned immediate byte offset, in the range 0 to 4095, defaulting to 0 and encoded in the "imm12" field.

For encoding T4: is an 8-bit unsigned immediate byte offset, in the range 0 to 255, defaulting to 0 if omitted, and encoded in the "imm8" field.

Alias Conditions

AliasOf variantIs preferred when
PUSH (single register)A1 (pre-indexed)P == '1' && U == '0' && W == '1' && Rn == '1101' && imm12 == '000000000100'
PUSH (single register)T4 (pre-indexed)Rn == '1101' && P == '1' && U == '0' && W == '1' && imm8 == '00000100'

Operation

if CurrentInstrSet() == InstrSet_A32 then if ConditionPassed() then EncodingSpecificOperations(); constant offset_addr = if add then (R[n] + imm32) else (R[n] - imm32); constant address = if index then offset_addr else R[n]; MemU[address,4] = if t == 15 then PCStoreValue() else R[t]; if wback then R[n] = offset_addr; else if ConditionPassed() then EncodingSpecificOperations(); constant offset_addr = if add then (R[n] + imm32) else (R[n] - imm32); constant address = if index then offset_addr else R[n]; MemU[address,4] = R[t]; if wback then R[n] = offset_addr;

Operational information

If CPSR.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.

Base Instructions
SIMD&FP Instructions
A32 Instructions by Encoding
T32 Instructions by Encoding
Shared Pseudocode
Proprietary Notice

Internal version only: isa v01_31, pseudocode v2024-03_rel ; Build timestamp: 2024-03-25T10:05

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