STRD (immediate)

Store Register Dual (immediate) calculates an address from a base register value and an immediate offset, and stores two words from two registers to memory. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses.

It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .

A1

if Rt<0> == '1' then UNPREDICTABLE; constant t = UInt(Rt); constant t2 = t+1; constant n = UInt(Rn); constant imm32 = ZeroExtend(imm4H:imm4L, 32); constant index = (P == '1'); constant add = (U == '1'); constant wback = (P == '0') || (W == '1'); if P == '0' && W == '1' then UNPREDICTABLE; if wback && (n == 15 || n == t || n == t2) then UNPREDICTABLE; if t2 == 15 then UNPREDICTABLE;

CONSTRAINED UNPREDICTABLE behavior

If t == 15 || t2 == 15, then one of the following behaviors must occur:

• The instruction is undefined.
• The instruction executes as NOP.
• The store instruction performs the store using the specified addressing mode but the value corresponding to R15 is unknown.

If wback && (n == t || n == t2), then one of the following behaviors must occur:

• The instruction is undefined.
• The instruction executes as NOP.
• The store instruction executes but the value stored is unknown.

If wback && n == 15, then one of the following behaviors must occur:

• The instruction is undefined.
• The instruction executes as NOP.
• The instruction executes without writeback of the base address.
• The instruction uses the addressing mode described in the equivalent immediate offset instruction.

If Rt<0> == '1', then one of the following behaviors must occur:

• The instruction is undefined.
• The instruction executes as NOP.
• The instruction executes with the additional decode: t<0> = '0'.
• The instruction executes with the additional decode: t2 = t.
• The instruction executes as described, with no change to its behavior and no additional side-effects. This does not apply when Rt == '1111'.

If P == '0' && W == '1', then one of the following behaviors must occur:

• The instruction is undefined.
• The instruction executes as NOP.
• The instruction executes as an LDRD using one of offset, post-indexed, or pre-indexed addressing.

T1

if P == '0' && W == '0' then SEE "Related encodings"; constant t = UInt(Rt); constant t2 = UInt(Rt2); constant n = UInt(Rn); constant imm32 = ZeroExtend(imm8:'00', 32); constant index = (P == '1'); constant add = (U == '1'); constant wback = (W == '1'); if wback && (n == t || n == t2) then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13 if n == 15 || t == 15 || t2 == 15 then UNPREDICTABLE;

CONSTRAINED UNPREDICTABLE behavior

If t == 15 || t2 == 15, then one of the following behaviors must occur:

• The instruction is undefined.
• The instruction executes as NOP.
• The store instruction performs the store using the specified addressing mode but the value corresponding to R15 is unknown.

If wback && (n == t || n == t2), then one of the following behaviors must occur:

• The instruction is undefined.
• The instruction executes as NOP.
• The store instruction executes but the value stored is unknown.

If wback && n == 15, then one of the following behaviors must occur:

• The instruction is undefined.
• The instruction executes as NOP.
• The instruction executes without writeback of the base address.
• The instruction uses the addressing mode described in the equivalent immediate offset instruction.

Assembler Symbols