STRD (register)

Store Register Dual (register) calculates an address from a base register value and a register offset, and stores two words from two registers to memory. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses.

A1

313029282726252423222120191817161514131211109876543210
!= 1111000PU0W0RnRt(0)(0)(0)(0)1111Rm
cond

Offset (P == 1 && W == 0)

STRD{<c>}{<q>} <Rt>, <Rt2>, [<Rn>, {+/-}<Rm>]

Post-indexed (P == 0 && W == 0)

STRD{<c>}{<q>} <Rt>, <Rt2>, [<Rn>], {+/-}<Rm>

Pre-indexed (P == 1 && W == 1)

STRD{<c>}{<q>} <Rt>, <Rt2>, [<Rn>, {+/-}<Rm>]!

if Rt<0> == '1' then UNPREDICTABLE; constant t = UInt(Rt); constant t2 = t+1; constant n = UInt(Rn); constant m = UInt(Rm); constant index = (P == '1'); constant add = (U == '1'); constant wback = (P == '0') || (W == '1'); if P == '0' && W == '1' then UNPREDICTABLE; if t2 == 15 || m == 15 then UNPREDICTABLE; if wback && (n == 15 || n == t || n == t2) then UNPREDICTABLE;

CONSTRAINED UNPREDICTABLE behavior

If t == 15 || t2 == 15, then one of the following behaviors must occur:

If wback && (n == t || n == t2), then one of the following behaviors must occur:

If wback && n == 15, then one of the following behaviors must occur:

If Rt<0> == '1', then one of the following behaviors must occur:

If P == '0' && W == '1', then one of the following behaviors must occur:

For more information about the constrained unpredictable behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors.

Assembler Symbols

<c>

See Standard assembler syntax fields.

<q>

See Standard assembler syntax fields.

<Rt>

Is the first general-purpose register to be transferred, encoded in the "Rt" field. This register must be even-numbered and not R14.

<Rt2>

Is the second general-purpose register to be transferred. This register must be <R(t+1)>.

<Rn>

Is the general-purpose base register, encoded in the "Rn" field. The PC can be used in the offset variant, but this is deprecated.

+/-

Specifies the index register is added to or subtracted from the base register, defaulting to + if omitted and encoded in U:

U +/-
0 -
1 +
<Rm>

Is the general-purpose index register, encoded in the "Rm" field.

Operation

if ConditionPassed() then EncodingSpecificOperations(); constant offset_addr = if add then (R[n] + R[m]) else (R[n] - R[m]); constant address = if index then offset_addr else R[n]; if IsAligned(address, 8) then bits(64) data; if BigEndian(AccessType_GPR) then data<63:32> = R[t]; data<31:0> = R[t2]; else data<31:0> = R[t]; data<63:32> = R[t2]; MemA[address,8] = data; else MemA[address,4] = R[t]; MemA[address+4,4] = R[t2]; if wback then R[n] = offset_addr;

Operational information

If CPSR.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.


Internal version only: isa v01_31, pseudocode v2024-03_rel ; Build timestamp: 2024-03-25T10:05

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