Store Register Exclusive Halfword derives an address from a base register value, stores a halfword from a register to the derived address if the executing PE has exclusive access to the memory at that address, and returns a status value of 0 if the store was successful, or of 1 if no store was performed.
For more information about support for shared memory see Synchronization and semaphores. For information about memory accesses see Memory accesses.
It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| != 1111 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 0 | Rn | Rd | (1) | (1) | 1 | 1 | 1 | 0 | 0 | 1 | Rt | ||||||||||||
| cond | |||||||||||||||||||||||||||||||
constant d = UInt(Rd); constant t = UInt(Rt); constant n = UInt(Rn); if d == 15 || t == 15 || n == 15 then UNPREDICTABLE; if d == n || d == t then UNPREDICTABLE;
If d == t, then one of the following behaviors must occur:
If d == n, then one of the following behaviors must occur:
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | Rn | Rt | (1) | (1) | (1) | (1) | 0 | 1 | 0 | 1 | Rd | |||||||||
constant d = UInt(Rd); constant t = UInt(Rt); constant n = UInt(Rn); // Armv8-A removes UNPREDICTABLE for R13 if d == 15 || t == 15 || n == 15 then UNPREDICTABLE; if d == n || d == t then UNPREDICTABLE;
If d == t, then one of the following behaviors must occur:
If d == n, then one of the following behaviors must occur:
For more information about the constrained unpredictable behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors.
| <c> |
| <q> |
| <Rt> |
Is the general-purpose register to be transferred, encoded in the "Rt" field. |
| <Rn> |
Is the general-purpose base register, encoded in the "Rn" field. |
Aborts and alignment
If a synchronous Data Abort exception is generated by the execution of this instruction:
A non halfword-aligned memory address causes an Alignment fault Data Abort exception to be generated, subject to the following rules:
If AArch32.ExclusiveMonitorsPass() returns FALSE and the memory address, if accessed, would generate a synchronous Data Abort exception, it is implementation defined whether the exception is generated.
if ConditionPassed() then EncodingSpecificOperations(); constant address = R[n]; if AArch32.ExclusiveMonitorsPass(address,2) then MemA[address,2] = R[t]<15:0>; R[d] = ZeroExtend('0', 32); else R[d] = ZeroExtend('1', 32);
If CPSR.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.
Internal version only: isa v01_31, pseudocode v2024-03_rel ; Build timestamp: 2024-03-25T10:05
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