STRH (immediate)

Store Register Halfword (immediate) calculates an address from a base register value and an immediate offset, and stores a halfword from a register to memory. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses.

It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 , T2 and T3 ) .

A1

if P == '0' && W == '1' then SEE "STRHT"; constant t = UInt(Rt); constant n = UInt(Rn); constant imm32 = ZeroExtend(imm4H:imm4L, 32); constant index = (P == '1'); constant add = (U == '1'); constant wback = (P == '0') || (W == '1'); if t == 15 then UNPREDICTABLE; if wback && (n == 15 || n == t) then UNPREDICTABLE;

CONSTRAINED UNPREDICTABLE behavior

If t == 15, then one of the following behaviors must occur:

• The instruction is undefined.
• The instruction executes as NOP.
• The store instruction performs the store using the specified addressing mode but the value corresponding to R15 is unknown.

If wback && n == t, then one of the following behaviors must occur:

• The instruction is undefined.
• The instruction executes as NOP.
• The store instruction executes but the value stored is unknown.

If wback && n == 15, then one of the following behaviors must occur:

• The instruction is undefined.
• The instruction executes as NOP.
• The instruction executes without writeback of the base address.
• The instruction uses the addressing mode described in the equivalent immediate offset instruction.

T1

constant t = UInt(Rt); constant n = UInt(Rn); constant imm32 = ZeroExtend(imm5:'0', 32); constant index = TRUE; constant add = TRUE; constant wback = FALSE;

T2

if Rn == '1111' then UNDEFINED; constant t = UInt(Rt); constant n = UInt(Rn); constant imm32 = ZeroExtend(imm12, 32); constant index = TRUE; constant add = TRUE; constant wback = FALSE; // Armv8-A removes UNPREDICTABLE for R13 if t == 15 then UNPREDICTABLE;

CONSTRAINED UNPREDICTABLE behavior

If t == 15, then one of the following behaviors must occur:

• The instruction is undefined.
• The instruction executes as NOP.
• The store instruction performs the store using the specified addressing mode but the value corresponding to R15 is unknown.

T3

if P == '1' && U == '1' && W == '0' then SEE "STRHT"; if Rn == '1111' || (P == '0' && W == '0') then UNDEFINED; constant t = UInt(Rt); constant n = UInt(Rn); constant imm32 = ZeroExtend(imm8, 32); constant index = (P == '1'); constant add = (U == '1'); constant wback = (W == '1'); // Armv8-A removes UNPREDICTABLE for R13 if t == 15 || (wback && n == t) then UNPREDICTABLE;

CONSTRAINED UNPREDICTABLE behavior

If t == 15, then one of the following behaviors must occur:

• The instruction is undefined.
• The instruction executes as NOP.
• The store instruction performs the store using the specified addressing mode but the value corresponding to R15 is unknown.

If wback && n == t, then one of the following behaviors must occur:

• The instruction is undefined.
• The instruction executes as NOP.
• The store instruction executes but the value stored is unknown.

Assembler Symbols