Store Register Halfword (register) calculates an address from a base register value and an offset register value, and stores a halfword from a register to memory. The offset register value can be shifted left by 0, 1, 2, or 3 bits. For information about memory accesses see Memory accesses.
It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 and T2 ) .
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| != 1111 | 0 | 0 | 0 | P | U | 0 | W | 0 | Rn | Rt | (0) | (0) | (0) | (0) | 1 | 0 | 1 | 1 | Rm | ||||||||||||
| cond | |||||||||||||||||||||||||||||||
if P == '0' && W == '1' then SEE "STRHT"; constant t = UInt(Rt); constant n = UInt(Rn); constant m = UInt(Rm); constant index = (P == '1'); constant add = (U == '1'); constant wback = (P == '0') || (W == '1'); constant (shift_t, shift_n) = (SRType_LSL, 0); if t == 15 || m == 15 then UNPREDICTABLE; if wback && (n == 15 || n == t) then UNPREDICTABLE;
If t == 15, then one of the following behaviors must occur:
If wback && n == t, then one of the following behaviors must occur:
If wback && n == 15, then one of the following behaviors must occur:
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 1 | 0 | 1 | 0 | 0 | 1 | Rm | Rn | Rt | ||||||
constant t = UInt(Rt); constant n = UInt(Rn); constant m = UInt(Rm); constant index = TRUE; constant add = TRUE; constant wback = FALSE; constant (shift_t, shift_n) = (SRType_LSL, 0);
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | != 1111 | Rt | 0 | 0 | 0 | 0 | 0 | 0 | imm2 | Rm | ||||||||||
| Rn | |||||||||||||||||||||||||||||||
if Rn == '1111' then UNDEFINED; constant t = UInt(Rt); constant n = UInt(Rn); constant m = UInt(Rm); constant index = TRUE; constant add = TRUE; constant wback = FALSE; constant (shift_t, shift_n) = (SRType_LSL, UInt(imm2)); // Armv8-A removes UNPREDICTABLE for R13 if t == 15 || m == 15 then UNPREDICTABLE;
If t == 15, then one of the following behaviors must occur:
For more information about the constrained unpredictable behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors.
| <c> |
| <q> |
| <Rt> |
Is the general-purpose register to be transferred, encoded in the "Rt" field. |
| +/- |
Specifies the index register is added to or subtracted from the base register, defaulting to + if omitted and
encoded in
|
| + |
Specifies the index register is added to the base register. |
| <Rm> |
Is the general-purpose index register, encoded in the "Rm" field. |
| <imm> |
If present, the size of the left shift to apply to the value from <Rm>, in the range 1-3. <imm> is encoded in imm2. If absent, no shift is specified and imm2 is encoded as 0b00. |
if ConditionPassed() then EncodingSpecificOperations(); constant offset = Shift(R[m], shift_t, shift_n, PSTATE.C); constant offset_addr = if add then (R[n] + offset) else (R[n] - offset); constant address = if index then offset_addr else R[n]; MemU[address,2] = R[t]<15:0>; if wback then R[n] = offset_addr;
If CPSR.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.
Internal version only: isa v01_31, pseudocode v2024-03_rel ; Build timestamp: 2024-03-25T10:05
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