Signed Extend Byte extracts an 8-bit value from a register, sign-extends it to 32 bits, and writes the result to the destination register. The instruction can specify a rotation by 0, 8, 16, or 24 bits before extracting the 8-bit value.
It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 and T2 ) .
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| != 1111 | 0 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 1 | 1 | 1 | 1 | Rd | rotate | (0) | (0) | 0 | 1 | 1 | 1 | Rm | ||||||||||
| cond | |||||||||||||||||||||||||||||||
constant d = UInt(Rd); constant m = UInt(Rm); constant rotation = UInt(rotate:'000'); if d == 15 || m == 15 then UNPREDICTABLE;
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 0 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | Rm | Rd | ||||
constant d = UInt(Rd); constant m = UInt(Rm); constant rotation = 0;
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | Rd | 1 | (0) | rotate | Rm | |||||||
constant d = UInt(Rd); constant m = UInt(Rm); constant rotation = UInt(rotate:'000'); // Armv8-A removes UNPREDICTABLE for R13 if d == 15 || m == 15 then UNPREDICTABLE;
For more information about the constrained unpredictable behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors.
| <c> |
| <q> |
| <Rd> |
Is the general-purpose destination register, encoded in the "Rd" field. |
| <Rm> |
Is the general-purpose source register, encoded in the "Rm" field. |
| <amount> |
Is the rotate amount,
encoded in
|
if ConditionPassed() then EncodingSpecificOperations(); constant rotated = ROR(R[m], rotation); R[d] = SignExtend(rotated<7:0>, 32);
If CPSR.DIT is 1, this instruction has passed its condition execution check, and does not use R15 as either its source or destination:
Internal version only: isa v01_31, pseudocode v2024-03_rel ; Build timestamp: 2024-03-25T10:05
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