UDF -- AArch32

The encodings for UDF used in this section are defined as permanently undefined. However:

It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 and T2 ) .

constant imm32 = ZeroExtend(imm12:imm4, 32); // imm32 is for assembly and disassembly only, and is ignored by hardware.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
1	1	0	1	1	1	1	0	imm8

constant imm32 = ZeroExtend(imm8, 32); // imm32 is for assembly and disassembly only, and is ignored by hardware.

constant imm32 = ZeroExtend(imm4:imm12, 32); // imm32 is for assembly and disassembly only, and is ignored by hardware.

<c>	For encoding A1: see Standard assembler syntax fields. <c> must be AL or omitted.
	For encoding T1 and T2: see Standard assembler syntax fields. Arm deprecates using any <c> value other than AL.

<q>	See Standard assembler syntax fields.

<imm>	For encoding A1: is a 16-bit unsigned immediate, in the range 0 to 65535, encoded in the "imm12:imm4" field. The PE ignores the value of this constant.
	For encoding T1: is a 8-bit unsigned immediate, in the range 0 to 255, encoded in the "imm8" field. The PE ignores the value of this constant.
	For encoding T2: is a 16-bit unsigned immediate, in the range 0 to 65535, encoded in the "imm4:imm12" field. The PE ignores the value of this constant.

if ConditionPassed() then EncodingSpecificOperations(); UNDEFINED;

Internal version only: isa v01_31, pseudocode v2024-03_rel ; Build timestamp: 2024-03-25T10:05