UXTAB -- AArch32

UXTAB

Unsigned Extend and Add Byte extracts an 8-bit value from a register, zero-extends it to 32 bits, adds the result to the value in another register, and writes the final result to the destination register. The instruction can specify a rotation by 0, 8, 16, or 24 bits before extracting the 8-bit value.

It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .

A1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
!= 1111				0	1	1	0	1	1	1	0	!= 1111				Rd				rotate		(0)	(0)	0	1	1	1	Rm
cond												Rn

A1

UXTAB{<c>}{<q>} {<Rd>,} <Rn>, <Rm> {, ROR #<amount>}

if Rn == '1111' then SEE "UXTB"; constant d = UInt(Rd); constant n = UInt(Rn); constant m = UInt(Rm); constant rotation = UInt(rotate:'000'); if d == 15 || m == 15 then UNPREDICTABLE;

T1

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
1	1	1	1	1	0	1	0	0	1	0	1	!= 1111				1	1	1	1	Rd				1	(0)	rotate		Rm
												Rn

T1

UXTAB{<c>}{<q>} {<Rd>,} <Rn>, <Rm> {, ROR #<amount>}

if Rn == '1111' then SEE "UXTB"; constant d = UInt(Rd); constant n = UInt(Rn); constant m = UInt(Rm); constant rotation = UInt(rotate:'000'); // Armv8-A removes UNPREDICTABLE for R13 if d == 15 || m == 15 then UNPREDICTABLE;

For more information about the constrained unpredictable behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors.

Assembler Symbols

<c>	See Standard assembler syntax fields.

<q>	See Standard assembler syntax fields.

<Rd>	Is the general-purpose destination register, encoded in the "Rd" field.

<Rn>	Is the first general-purpose source register, encoded in the "Rn" field.

<Rm>	Is the second general-purpose source register, encoded in the "Rm" field.

Is the rotate amount, encoded in rotate:

rotate	<amount>
00	(omitted)
01	8
10	16
11	24

Operation

if ConditionPassed() then EncodingSpecificOperations(); constant rotated = ROR(R[m], rotation); R[d] = R[n] + ZeroExtend(rotated<7:0>, 32);

Operational information

If CPSR.DIT is 1, this instruction has passed its condition execution check, and does not use R15 as either its source or destination:

The execution time of this instruction is independent of:
- The values of the data supplied in any of its registers.
- The values of the NZCV flags.
The response of this instruction to asynchronous exceptions does not vary based on:
- The values of the data supplied in any of its registers.
- The values of the NZCV flags.

Internal version only: isa v01_31, pseudocode v2024-03_rel ; Build timestamp: 2024-03-25T10:05