UXTB16 -- AArch32

Unsigned Extend Byte 16 extracts two 8-bit values from a register, zero-extends them to 16 bits each, and writes the results to the destination register. The instruction can specify a rotation by 0, 8, 16, or 24 bits before extracting the 8-bit values.

It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .

constant d = UInt(Rd); constant m = UInt(Rm); constant rotation = UInt(rotate:'000'); if d == 15 || m == 15 then UNPREDICTABLE;

constant d = UInt(Rd); constant m = UInt(Rm); constant rotation = UInt(rotate:'000'); // Armv8-A removes UNPREDICTABLE for R13 if d == 15 || m == 15 then UNPREDICTABLE;

Assembler Symbols

Operation

if ConditionPassed() then EncodingSpecificOperations(); constant rotated = ROR(R[m], rotation); R[d]<15:0> = ZeroExtend(rotated<7:0>, 16); R[d]<31:16> = ZeroExtend(rotated<23:16>, 16);

Operational information

If CPSR.DIT is 1, this instruction has passed its condition execution check, and does not use R15 as either its source or destination:

The execution time of this instruction is independent of:
- The values of the data supplied in any of its registers.
- The values of the NZCV flags.
The response of this instruction to asynchronous exceptions does not vary based on:
- The values of the data supplied in any of its registers.
- The values of the NZCV flags.

Internal version only: isa v01_31, pseudocode v2024-03_rel ; Build timestamp: 2024-03-25T10:05

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
!= 1111				0	1	1	0	1	1	0	0	1	1	1	1	Rd				rotate		(0)	(0)	0	1	1	1	Rm
cond

<Rm>	For encoding A1: is the general-purpose source register, encoded in the "Rm" field.
	For encoding T1: is the second general-purpose source register, encoded in the "Rm" field.