Vector Absolute Compare Greater Than takes the absolute value of each element in a vector, and compares it with the absolute value of the corresponding element of a second vector. If the first is greater than the second, the corresponding element in the destination vector is set to all ones. Otherwise, it is set to all zeros.
The operands and result can be quadword or doubleword vectors. They must all be the same size.
The operand vector elements are floating-point numbers. The result vector elements are the same size as the operand vector elements.
Depending on settings in the CPACR, NSACR, and HCPTR registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.
This instruction is used by the pseudo-instruction VACLT.
It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 1 | 1 | 0 | 0 | 1 | 1 | 0 | D | 1 | sz | Vn | Vd | 1 | 1 | 1 | 0 | N | Q | M | 1 | Vm | |||||||||
| op | |||||||||||||||||||||||||||||||
if Q == '1' && (Vd<0> == '1' || Vn<0> == '1' || Vm<0> == '1') then UNDEFINED; if sz == '1' && !IsFeatureImplemented(FEAT_FP16) then UNDEFINED; constant or_equal = (op == '0'); constant integer esize = 32 >> UInt(sz); constant d = UInt(D:Vd); constant n = UInt(N:Vn); constant m = UInt(M:Vm); constant elements = 64 DIV esize; constant regs = if Q == '0' then 1 else 2;
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | D | 1 | sz | Vn | Vd | 1 | 1 | 1 | 0 | N | Q | M | 1 | Vm | |||||||||
| op | |||||||||||||||||||||||||||||||
if Q == '1' && (Vd<0> == '1' || Vn<0> == '1' || Vm<0> == '1') then UNDEFINED; if sz == '1' && !IsFeatureImplemented(FEAT_FP16) then UNDEFINED; if sz == '1' && InITBlock() then UNPREDICTABLE; constant or_equal = (op == '0'); constant integer esize = 32 >> UInt(sz); constant d = UInt(D:Vd); constant n = UInt(N:Vn); constant m = UInt(M:Vm); constant elements = 64 DIV esize; constant regs = if Q == '0' then 1 else 2;
If sz == '1' && InITBlock(), then one of the following behaviors must occur:
| <c> |
For encoding A1: see Standard assembler syntax fields. This encoding must be unconditional. |
|
For encoding T1: see Standard assembler syntax fields. |
| <q> |
| <dt> |
Is the data type for the elements of the vectors,
encoded in
|
| <Qd> |
Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field as <Qd>*2. |
| <Qn> |
Is the 128-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field as <Qn>*2. |
| <Qm> |
Is the 128-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field as <Qm>*2. |
| <Dd> |
Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field. |
| <Dn> |
Is the 64-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field. |
| <Dm> |
Is the 64-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field. |
if ConditionPassed() then EncodingSpecificOperations(); CheckAdvSIMDEnabled(); constant FPCR_Type fpcr = StandardFPCR(); for r = 0 to regs-1 for e = 0 to elements-1 constant op1 = FPAbs(Elem[D[n+r],e,esize], fpcr); constant op2 = FPAbs(Elem[D[m+r],e,esize], fpcr); boolean test_passed; if or_equal then test_passed = FPCompareGE(op1, op2, fpcr); else test_passed = FPCompareGT(op1, op2, fpcr); Elem[D[d+r],e,esize] = if test_passed then Ones(esize) else Zeros(esize);
Internal version only: isa v01_31, pseudocode v2024-03_rel ; Build timestamp: 2024-03-25T10:05
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