Convert between double-precision and single-precision does one of the following:
Depending on settings in the CPACR, NSACR, HCPTR, and FPEXC registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.
It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| != 1111 | 1 | 1 | 1 | 0 | 1 | D | 1 | 1 | 0 | 1 | 1 | 1 | Vd | 1 | 0 | 1 | x | 1 | 1 | M | 0 | Vm | |||||||||
| cond | size | ||||||||||||||||||||||||||||||
constant double_to_single = (size == '11'); constant d = if double_to_single then UInt(Vd:D) else UInt(D:Vd); constant m = if double_to_single then UInt(M:Vm) else UInt(Vm:M);
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 1 | 0 | 1 | 1 | 1 | 0 | 1 | D | 1 | 1 | 0 | 1 | 1 | 1 | Vd | 1 | 0 | 1 | x | 1 | 1 | M | 0 | Vm | ||||||
| size | |||||||||||||||||||||||||||||||
constant double_to_single = (size == '11'); constant d = if double_to_single then UInt(Vd:D) else UInt(D:Vd); constant m = if double_to_single then UInt(M:Vm) else UInt(Vm:M);
| <c> |
| <q> |
| <Sd> |
Is the 32-bit name of the SIMD&FP destination register, encoded in the "Vd:D" field. |
| <Dm> |
Is the 64-bit name of the SIMD&FP source register, encoded in the "M:Vm" field. |
| <Dd> |
Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field. |
| <Sm> |
Is the 32-bit name of the SIMD&FP source register, encoded in the "Vm:M" field. |
if ConditionPassed() then EncodingSpecificOperations(); CheckVFPEnabled(TRUE); if double_to_single then S[d] = FPConvert(D[m], EffectiveFPCR(), 32); else D[d] = FPConvert(S[m], EffectiveFPCR(), 64);
Internal version only: isa v01_31, pseudocode v2024-03_rel ; Build timestamp: 2024-03-25T10:05
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