Vector Extract extracts elements from the bottom end of the second operand vector and the top end of the first, concatenates them and places the result in the destination vector.
The elements of the vectors are treated as being 8-bit fields. There is no distinction between data types.
The following figure shows an example of the operation of VEXT doubleword operation for imm = 3.
Depending on settings in the CPACR, NSACR, and HCPTR registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.
This instruction is used by the pseudo-instruction VEXT (multibyte elements).
It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | 1 | 1 | 1 | 0 | 0 | 1 | 0 | 1 | D | 1 | 1 | Vn | Vd | imm4 | N | Q | M | 0 | Vm |
if Q == '1' && (Vd<0> == '1' || Vn<0> == '1' || Vm<0> == '1') then UNDEFINED; if Q == '0' && imm4<3> == '1' then UNDEFINED; constant quadword_operation = (Q == '1'); constant integer position = 8 * UInt(imm4); constant d = UInt(D:Vd); constant n = UInt(N:Vn); constant m = UInt(M:Vm);
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | D | 1 | 1 | Vn | Vd | imm4 | N | Q | M | 0 | Vm |
if Q == '1' && (Vd<0> == '1' || Vn<0> == '1' || Vm<0> == '1') then UNDEFINED; if Q == '0' && imm4<3> == '1' then UNDEFINED; constant quadword_operation = (Q == '1'); constant integer position = 8 * UInt(imm4); constant d = UInt(D:Vd); constant n = UInt(N:Vn); constant m = UInt(M:Vm);
<c> |
For encoding A1: see Standard assembler syntax fields. This encoding must be unconditional. |
For encoding T1: see Standard assembler syntax fields. |
<q> |
<Qd> |
Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field as <Qd>*2. |
<Qn> |
Is the 128-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field as <Qn>*2. |
<Qm> |
Is the 128-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field as <Qm>*2. |
<Dd> |
Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field. |
<Dn> |
Is the 64-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field. |
<Dm> |
Is the 64-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field. |
if ConditionPassed() then EncodingSpecificOperations(); CheckAdvSIMDEnabled(); if quadword_operation then Q[d>>1] = (Q[m>>1]:Q[n>>1])<position+127:position>; else D[d] = (D[m]:D[n])<position+63:position>;
If CPSR.DIT is 1 and this instruction passes its condition execution check:
Internal version only: isa v01_31, pseudocode v2024-03_rel ; Build timestamp: 2024-03-25T10:05
Copyright © 2010-2024 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.