Vector move Insertion. This instruction copies the lower 16 bits of the 32-bit source SIMD&FP register into the upper 16 bits of the 32-bit destination SIMD&FP register, while preserving the values in the remaining bits.
Depending on settings in the CPACR, NSACR, HCPTR, and FPEXC registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.
It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | D | 1 | 1 | 0 | 0 | 0 | 0 | Vd | 1 | 0 | 1 | 0 | 1 | 1 | M | 0 | Vm | ||||||
if !IsFeatureImplemented(FEAT_FP16) then UNDEFINED; if FPSCR.Len != '000' || FPSCR.Stride != '00' then UNDEFINED; constant d = UInt(Vd:D); constant m = UInt(Vm:M);
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | D | 1 | 1 | 0 | 0 | 0 | 0 | Vd | 1 | 0 | 1 | 0 | 1 | 1 | M | 0 | Vm | ||||||
if InITBlock() then UNPREDICTABLE; if !IsFeatureImplemented(FEAT_FP16) then UNDEFINED; if FPSCR.Len != '000' || FPSCR.Stride != '00' then UNDEFINED; constant d = UInt(Vd:D); constant m = UInt(Vm:M);
If InITBlock(), then one of the following behaviors must occur:
| <q> |
| <Sd> |
Is the 32-bit name of the SIMD&FP destination register, encoded in the "Vd:D" field. |
| <Sm> |
Is the 32-bit name of the SIMD&FP source register, encoded in the "Vm:M" field. |
if ConditionPassed() then EncodingSpecificOperations(); CheckVFPEnabled(TRUE); S[d]<31:16> = H[m];
Internal version only: isa v01_31, pseudocode v2024-03_rel ; Build timestamp: 2024-03-25T10:05
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